Memory device with fast extended data out (EDO) mode and methods

Details Memory device with fast extended data out (EDO) mode and methods Memory device with fast extended data out (EDO) mode and methods

1996-09-11

1998-04-07

Nelms, David C.

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

365203, 365235, 3652385, G11C 800

Patent

active

057372764

ABSTRACT:
A memory device having normal and extended data out (EDO). modes includes an array of memory cells arranged in plurality of rows and columns, first and second data latches which store data, a column address input which receives a column address signal, and a column address strobe input which receives a column address strobe signal. First latch control means, responsive to said column address input and to the column address strobe input, electrically couples one memory cell in the array of memory cells and the first data latch when a column address signal is asserted at the column address input and electrically decouples the one memory cell and the first data latch when a column address strobe signal is asserted at the column address strobe input, thereby latching data present in the one memory cell prior to assertion of the column address strobe signal in the first data latch. Second latch control means, responsive to the column address strobe input, electrically couples the first data latch and the second data latch when a column address strobe signal is asserted at the column address strobe input and electrically decouples the first data latch and the second data latch when a column address strobe signal is deasserted at the column address strobe input, thereby latching data present in the first data latch prior to deassertion of the column address strobe signal in the second data latch.

REFERENCES:
patent: 5436865 (1995-07-01), Kitazawa
patent: 5457659 (1995-10-01), Schaefer
patent: 5532961 (1996-07-01), Mori et al.
patent: 5610864 (1997-03-01), Manning

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