Memory device with error correction capability and...

Details Memory device with error correction capability and... Memory device with error correction capability and...

2011-04-19

2011-04-19

Chase, Shelly A (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

Reexamination Certificate

active

07930615

ABSTRACT:
A memory device comprises a memory array and error correction circuitry coupled to the memory array. The memory device is configured to perform a partial word write operation in which an error correction code encode process for the given retrieved word is initiated prior to completion of an error correction code decode process for the given retrieved word based on an assumption that the error correction code decode process will not indicate an error in the given retrieved word. If the error correction code decode process when completed indicates an error in the given retrieved word, the error in the given retrieved word is corrected in the error correction circuitry, and the error correction code encode process is restarted using the corrected word. The error correction code decode process and an associated correct process are thereby removed from a critical timing path of the partial word write operation.

REFERENCES:
patent: 7254763 (2007-08-01), Aadsen et al.
patent: 7275200 (2007-09-01), Leung
patent: 7392456 (2008-06-01), Leung et al.
patent: 7610542 (2009-10-01), Nagai
patent: 2008/0168331 (2008-07-01), Vogelsang et al.
PCT International Application No. PCT/US07/67502 filed in the name of R.A. Kohler et al. on Apr. 26, 2007 and entitled “Memory Device with Error Correction Capability and Efficient Partial Word Write Operation.”

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