Memory device with dual timing and signal latching control

Details Memory device with dual timing and signal latching control Memory device with dual timing and signal latching control

1997-07-18

2000-02-29

Lane, Jack A.

Electrical computers and digital processing systems: memory

Addressing combined with specific memory configuration or...

For multiple memory modules

711105, G06F 1200

Patent

active

060322209

ABSTRACT:
In a packetized memory device, pipelined row and column address paths receive row and column addresses from an address capture circuit. Each of the row and column address paths includes a respective address latch that latches the row or column address from the address capture circuitry, thereby freeing the address capture circuitry to capture a subsequent address. The column path also includes a set of bank address latches so that bank addresses can be pipelined synchronously with column addresses. The latched row and column addresses are then provided to a combining circuit. Additionally, redundant row and column circuits receive these latched addresses and indicate to the combining circuit whether or not to substitute a redundant row. The combining circuit, responsive to a strobe then transfers the redundant row address or latched row address to a decoder to activate the array. The bank address latches also activate a selected bank responsive to the strobe.

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Description literature entitled, "400 MHz SLDRAM, 4M.times.16 SLDRAM Pipelined, Eight Bank, 2.5 V Operation", pp. 1-22.
"Draft Standard for a High-Speed Memory Interface (SyncLink)", Microprocessor and Microcomputer Standards Subcommittee of the IEEE Computer Society, Copyright 1996 by the Institute of Electrical and Electronics Engineers, Inc., New York, NY, pp. 1-56.

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