Static information storage and retrieval – Read/write circuit – Differential sensing
Patent
1997-07-21
1999-09-07
Nelms, David
Static information storage and retrieval
Read/write circuit
Differential sensing
365205, 365206, 365226, 36518709, G11C 702
Patent
active
059497297
ABSTRACT:
A sense circuit for a DRAM circuit in which small potential difference between bit lines and is produced when the memory cell in the memory cell array is connected to one of the bit lines. The sense circuit starts sensing and amplifying when the sense starting signal changes to "L" level. An inverter provides a sense activating signal of "H" level to an NMOS device, while another inverter provides a sense activating signal of "L" level to a PMOS device. Sense amplifiers 33 are then activated and the potential difference between the bit lines and is amplified. Since the "L" level of the sense activating signal that is generated by the inverter is set to a value midway between a first power potential VSS and a second power potential VCC, the conductive resistance of the PMOS device is higher than that of a conventional circuit supplied with the first power potential VSS. Consequently, the voltage drop due to the PMOS device increases and power noise is reduced.
REFERENCES:
patent: 5418750 (1995-05-01), Shiratake et al.
patent: 5418753 (1995-05-01), Seki
patent: 5446694 (1995-08-01), Tanaka et al.
patent: 5539701 (1996-07-01), Shimizu
patent: 5619465 (1997-04-01), Nomura et al.
Fukudome Kazukiyo
Hirota Akihiro
Suyama Junichi
Nelms David
Nguyen Tuan T.
OKI Electric Industry Co., Ltd.
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