Memory device with control circuit for regulating power...

Static information storage and retrieval – Read/write circuit – Including reference or bias voltage generator

Reexamination Certificate

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Reexamination Certificate

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07366036

ABSTRACT:
A Local Dynamic Power Controller (LDPC) generates and deliver to a load a full swing voltage supply signal and a reduced swing voltage supply signal. Both the full and reduce voltage supply signals are generated from a single power supply. The full swing voltage supply signal is supplied when the load is in full operational mode whereas the reduce voltage supply signal is provided when the load is in a sleep mode. As a consequence, power dissipated in the load is reduced.

REFERENCES:
patent: 6034563 (2000-03-01), Mashiko
patent: 6097113 (2000-08-01), Teraoka et al.
patent: 6222410 (2001-04-01), Seno
patent: 6329874 (2001-12-01), Ye et al.
patent: 6333571 (2001-12-01), Teraoka et al.
patent: 6380798 (2002-04-01), Mizuno et al.
patent: 6567319 (2003-05-01), Sato et al.
patent: 6657911 (2003-12-01), Yamaoka et al.
patent: 6714461 (2004-03-01), Matsumoto et al.
patent: 6794914 (2004-09-01), Sani et al.
patent: 6999370 (2006-02-01), Luk et al.
Kawaguchi, Hiroshi, et al., A Reduced Clock-Swing Flip-Flop (RCSFF) for 63% Power Reduction, IEEE Journal of Solid-State Circuits, vol. 33, No. 5, pp. 807-811 (May 1998).
Tschanz, James W., et al., Dynamic Sleep Transistor and Body Bias for Active Leakage Power Control of Microprocessors, IEEE Journal of Solid-State Circuits, vol. 38, No. 11, pp. 1838-1845 (Nov. 2003).
Kim, Chris H., et al., Dynamic Vt SRAM: A Leakage Tolerant Cache Memory for Low Voltage Micropressors, ACM, ISLPED '02, Monterey, Calif., pp. 251-254 (Aug. 12-14, 2002).
Strolle, A.G.M., et cl., New clock-Gating Techniques for Low-Power Flip-flops, ACM, ISLPED '00, Rapallo, Italy, pp. 114-119 (2000).
Elakkumanan, Praveen, et al., NC-SRAM—A Low Leakage Memory Circuit for Ultra Deep Submicron Designs, IEEE, pp. 3-6 (2003).
Agarwal, Amit, et al., A Single-Vt Low-Leakage Gated-Ground Cache for Deep Submicron, IEEE, pp. 319-328 (2003).
Powell, Michael, et al., Gated-Vdd: A Circuit Technique to Reduce Leakage in Deep-Submicron Cache Memories, ACM, ISLPED '00, Rapallo, Italy,6 pages (2000).

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