Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
1998-09-03
2001-02-20
Lane, Jack A. (Department: 2751)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S154000
Reexamination Certificate
active
06192446
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to memory devices, and more particularly, to a memory device having a command buffer for storing commands to be executed by the memory device independent of its external command input signals.
2. Description of the Related Art
Memory devices, such as dynamic random access memories (DRAM), synchronous dynamic random access memories (SDRAM), static random access memories (SRAM), and the like have been widely used to provide random memory for use by a microprocessor in a computer system. Typically, a series of commands are issued to the memory device to access its storage locations (i.e., cells) to read or write data. The access may be a discrete single cell access, or alternatively the access might read or write to a plurality of cells with a single command (e.g., a burst access or block access). In response to the series of commands, the memory device reads or writes the appropriate data.
Typically a memory controller receives memory requests from the microprocessor and issues memory access commands to the memory device. The memory controller provides row and column addresses to the memory device to specify the desired memory cell or cells in the system memory to be accessed based on the memory request. The memory controller also provides one or more logic signals that communicate the type of command (e.g., read or write, etc.) to the memory device. For each command, the memory controller must drive the address and logic signal lines to communicate the command to the memory device.
Driving the address and logic signals for each command consumes electrical power. In some computer systems, such as notebook systems, it is important to conserve electrical power, when possible, to extend the operating time provided by the battery. One power conservation technique involves de-energizing devices or portions of a memory device when it is not being accessed. For example, memory devices often include two or more banks of storage cells that may be independently accessed. To conserve power, logic supporting the unused bank may be powered down. Typically, the microprocessor is constantly reading from or writing to the memory device. Although, unused portions of the memory device may be powered down to conserve power, power is still required to drive the external address lines and logic signals for each command.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
SUMMARY OF THE INVENTION
One aspect of the present invention is seen in a memory device including a memory array, a plurality of external lines, a command buffer, and control logic. The plurality of external lines is adapted for receiving an external command. The command buffer is adapted to store at least one command buffer entry. The control logic is coupled to the plurality of external lines and the command buffer. The control logic is adapted to access the memory array based on one of the command buffer entry and the external command.
Another aspect of the present invention is seen in a method for providing commands to a memory device. The memory device includes a command buffer, control logic and a memory array. The method includes reading a first buffered command from the command buffer. The first buffered command is provided to the control logic. The memory array is accessed based on the first buffered command.
REFERENCES:
patent: 6032220 (2000-02-01), Martin et al.
Derner Scott J.
Kurth Casey R.
Mullarkey Patrick J.
Lane Jack A.
Micro)n Technology, Inc.
Williams, Morsan & Amerson, P.C.
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