Memory device with column select being variably delayed

Details Memory device with column select being variably delayed Memory device with column select being variably delayed

2006-04-25

2006-04-25

Lane, Jack A. (Department: 2188)

Static information storage and retrieval

Read/write circuit

Signals

C365S230060

Reexamination Certificate

active

07035150

ABSTRACT:
A memory device (10) includes an array (12) of memory cells arranged in rows and columns. Preferably, each memory cell includes a pass transistor coupled to a storage capacitor. A row decoder is coupled to rows of memory cells while a column decoder (14) is coupled to columns of the memory cells. The column decoder (14) includes an enable input. A variable delay (32) has an output coupled to the enable input of the column decoder (14). The variable delay (32) receives an indication (R/W′) of whether a current cycle is a read cycle or a write cycle. In the preferred embodiment, a signal provided at the output of the variable delay (32) is delayed if the current cycle is a read cycle compared to if the current cycle is a write cycle.

REFERENCES:
patent: 6134179 (2000-10-01), Ooishi
patent: 6269031 (2001-07-01), Fukuhara
Wuensche, et al. “A 110nm 512 Mb DDR Dram with Vertical Transistor Trench Cell,” 2002 Symposium on VLSI Circuits, Digest of Technical Papers, Jun. 13-15, 2002, pp. 114-115.

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