Memory device with built-in test function and method for...

Details Memory device with built-in test function and method for... Memory device with built-in test function and method for...

2007-10-23

2007-10-23

Nguyen, Van Thu (Department: 2824)

Static information storage and retrieval

Read/write circuit

Testing

C365S200000

Reexamination Certificate

active

11146339

ABSTRACT:
A test circuit employs hardware to test a memory cell in a memory block. The address of an error cell detected is stored in a first or second error address register. Access made by a processor to the address of the error cell would be detected by a first or second address comparator. Data is then written to a first or second correction register, which serves as an alternative cell, or data is read from one of the registers.

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Office Action for corresponding Japanese Patent Application No. 2003-377503 with English abstract dated May 23, 2006.
International Preliminary Report on Patentability for International Application No. PCT/JP2004/010860 mailed Aug. 3, 2006.
Japanese Office Action for Application No. 2003-377503 Date: Sep. 5, 2006.
Office Action for corresponding Chinese Patent Application No. 200480001746.9 issued Jun. 8, 2007 with English translation.

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