Memory device with barrier layer

Details Memory device with barrier layer Memory device with barrier layer

2006-07-21

2010-10-19

Booth, Richard A. (Department: 2812)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257SE27078

Reexamination Certificate

active

07816724

ABSTRACT:
A memory device (100) may include a substrate (110), a dielectric layer (210) formed on the substrate (110) and a charge storage element (220) formed on the dielectric layer (210). The memory device (100) may also include an inter-gate dielectric (230) formed on the charge storage element (220), a barrier layer (240) formed on the inter-gate dielectric (230) and a control gate (250) formed on the barrier layer (240). The barrier layer (240) prevents reaction between the control gate (250) and the inter-gate dielectric (230).

REFERENCES:
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patent: 2005/0194627 (2005-09-01), Nomoto et al.
International Search Report and Written Opinion for PCT Application No. PCT/US2006/028539, mailed Dec. 8, 2006, 12 pages.
Co-pending U.S. Appl. No. 11/135,42, filed May 24, 2005, entitled “Interface Layer Between Dual Polycrystalline Silicon Layers”, Mark Ramsbey et al., 20 pages.

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