Memory device with an ECC system

Details Memory device with an ECC system Memory device with an ECC system

2011-06-14

2011-06-14

Torres, Joseph D (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S784000, C714S785000

Reexamination Certificate

active

07962838

ABSTRACT:
A memory device has an error detection and correction system constructed on a Galois finite field. The error detection and correction system includes calculation circuits for calculating the finite field elements based on syndromes obtained from read data and searching error locations, the calculation circuits having common circuits, which are used in a time-sharing mode under the control of internal clocks.

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U.S. Appl. No. 12,524,880, filed Jul. 29, 2009, Haruki Toda.

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