Static information storage and retrieval – Read/write circuit – Differential sensing
Reexamination Certificate
2000-02-03
2001-01-09
Phan, Trong (Department: 2818)
Static information storage and retrieval
Read/write circuit
Differential sensing
C365S226000
Reexamination Certificate
active
06172924
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to electronic circuits and in particular to a memory device with a sense amplifier.
BACKGROUND OF THE INVENTION
In the electronics industry, device manufacturers design and produce commodity parts that are capable of operating in a variety of electronic systems that have different electronic specifications. For example, dynamic random access memory (DRAM) devices are designed for use in electronic systems with a wide range of power supply voltage. To keep pace with changes in system specifications, device manufacturers face the difficult task of designing new parts that operate over a wider range of conditions.
A DRAM device is comprised of an array of individual memory cells. Typically, each memory cell comprises a capacitor capable of holding a charge and an access transistor for accessing the capacitor charge. The charge is representative of a data bit and can be either a high voltage or a low voltage. Data can be either stored in the memory cells during a write mode, or data may be retrieved from the memory cells during a read mode. The data is transmitted on signal lines, referred to as digit lines, which are coupled to input/output lines through transistors used as switching devices. For each bit of data stored, its true logic state is available on an I/O line and its complementary logic state is available on an I/O complement line. Thus, each memory cell has two digit lines, digit and digit complement.
Typically, the memory cells are arranged in an array and each cell has an address identifying its location in the array. The array comprises a configuration of intersecting rows and a memory cell is associated with each intersection. In order to read from or write to a cell, the particular cell in question must be selected, or addressed. The address for the selected cell is represented by input signals to a row decoder and to a column decoder. The row decoder activates a word line in response to the row address. The selected word line activates the access transistors for each of the memory cells in communication with the selected word line. The column decoder selects a digit line pair in response to the column address. For a read operation the selected word line activates the access transistors for a given row address, and data is latched to the digit line pairs.
Conventional dynamic memory devices use memory cells fabricated as capacitors in an integrated circuit to store data. That is, a logical “1” is stored as a charge on the capacitor and the capacitor is discharged for a logical “0”. The pairs of digit lines are fabricated as metal lines on the integrated circuit and connected to the memory cells for transmitting data stored in the memory cells. Sense amplifiers are utilized to sense small differentials on the digit lines and drive the digit lines to full power supply rails for either reading the memory cells or writing thereto.
Typically, a sense amplifier includes a pair of n-channel transistors having a cross-coupled gate and drain configuration. Due to the positive feedback of this configuration, the sense amplifier senses slight changes in the voltages on the digit and digit complement lines and produces full logic values on the digit lines based on the slight voltage differential. The source of each transistor is coupled to a pull down device, which, in operation drives the source of the transistors to ground thus allowing the sense amplifier to amplify the small changes in voltage on the digit and digit complement lines.
Conventionally, the pull down device of an n-channel sense amplifier comprises an n-channel MOS transistor. Unfortunately, conventional pull down devices do not function properly over the wider range of power supply voltages demanded by newer systems. At low supply voltages, the current in a typical pull down device is not sufficient to allow the sense amplifier to settle quick enough to produce an accurate reading at the digit lines. Further, at high power supply voltages, the pull down device draws too much current and drives the common source and the drains of both transistors to ground before the digit lines can reach the proper voltages.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a memory device which functions properly over a wide range of power supply voltage.
SUMMARY OF THE INVENTION
A memory device with a sense amplifier is described which operates acceptably over a wide range of power supply voltages. In one embodiment, the present invention describes a circuit for a sense amplifier for use with a memory device that is operable over varied power supply voltages. The circuit includes two devices that are controlled by a selector. The first device drives the sense amplifier with a first current level. The second device drives the sense amplifier with a second current level, different from the first current level. The selector is coupled to the first and second devices so as to selectively couple devices to the sense amplifier based on a power supply voltage of the memory device.
In one embodiment the devices are n-channel MOS transistors that function as pull-down devices for an n-sense amplifier. The pull-down devices may have different widths so as to drive the sense amplifier with different current levels. Alternatively, the pull-down devices may have similar widths and be selectively coupled alone or in combination to the sense amplifier to produce an acceptable current to drive the sense amplifier.
In further embodiments, the selector comprises a Schmitt trigger that produces a signal that selectively activates the devices based on the power supply voltage. The Schmitt trigger receives a signal that is proportional to the supply voltage and compares the signal with a threshold value of the Schmitt trigger. In further embodiments, the selector circuit comprises logic gates coupled between the Schmitt trigger and the first and second devices so as to produce signals to selectively activate the devices.
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Cutler Kacey
Gilliam Gary R.
Ochoa Roland
Renfro Steve G.
Schneider Craig E.
Micro)n Technology, Inc.
Phan Trong
Schwegman, Lundberg, Woessner & Kluth, P.A .
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