Memory device with a plurality of reference cells on a bit line

Details Memory device with a plurality of reference cells on a bit line Memory device with a plurality of reference cells on a bit line

2008-01-01

2008-01-01

Dinh, Son (Department: 2824)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S185050, C365S185200, C365S211000

Reexamination Certificate

active

11250005

ABSTRACT:
In accordance with one embodiment of the invention, a memory device comprises an array of memory cells arranged into word lines and bit lines, with a sense amplifier and a plurality of reference cells for each bit line. The sense amplifier for a bit line compares the output of a memory cell for that bit line with the output of one of the plurality of reference cells for that bit line.

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patent: 2005/0286299 (2005-12-01), Tomita et al.
patent: 2006/0044886 (2006-03-01), Iwata et al.

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