Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
2006-12-05
2006-12-05
Padmanabhan, Mano (Department: 2189)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
Reexamination Certificate
active
07146456
ABSTRACT:
A dynamic random access memory device is capable of converting from a full density memory device to a reduced density memory device. The reduced density memory device compensates for cell failures in a plurality of cell blocks, regardless of the location of the cell failures. The memory device includes a row address mapping fuse for selectively determining row address combinations capable of storing data bits. A row address mapping logic is coupled to the row address mapping fuse and is capable of routing data bits to the address combinations capable of storing data bits.
REFERENCES:
patent: 5583813 (1996-12-01), Dosaka et al.
patent: 6038382 (2000-03-01), Kanazawa
patent: 6044029 (2000-03-01), Shore
patent: 6078542 (2000-06-01), Tomishima
patent: 6519201 (2003-02-01), Cowles et al.
patent: 6549476 (2003-04-01), Pinney
patent: 6556497 (2003-04-01), Cowles et al.
patent: 6567287 (2003-05-01), Scheuerlein
patent: 6586300 (2003-07-01), Hummler et al.
patent: 6603694 (2003-08-01), Frankowsky et al.
patent: 6807114 (2004-10-01), Keeth et al.
Ars Technica, LLC webpage entitled “ RAM Guide: Part I: DRAM and SRAM Basics—Storage Theory”, 5 pgs; available at www.arstechnica.com, Jon “Hannibal” Stokes, © 1998-2003.
Ars Technica, LLC webpage entitled “RAM Guide: Part I: DRAM and SRAM Basics—RAM Chips”, 4 pgs; available at www.arstechnica.com, Jon “Hannibal” Stokes, © 1998-2003.
Ars Technica, LLC webpage entitled “RAM Guide: Part I: DRAM and SRAM Basics—RAM chips”, 6 pgs; available at www.arstechnica.com, Jon “Hannibal” Stokes, © 1998-2003.
Ars Technica, LLC webpage entilted “Ars Technica RAM Guide Part II: Asynchronous and Synchronous DRAM”, 5 pgs; available at www.arstechnica.com, Jon “Hannibal” Stokes, © 1998-2003.
Ars Technica, LLC webpage entitled “Ars Technica RAM Guide, Part III: DDR DRAM and RAMBUS”, 5 pgs; available at www.arstechnica.com, Jon “Hannibal” Stokes, © 1998-2003.
Dicke Billig & Czaja, PLLC
Infineon Technologies North America Corp.
Ko Daniel
Padmanabhan Mano
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