Memory device with a data output buffer and the control method t

Details Memory device with a data output buffer and the control method t Memory device with a data output buffer and the control method t

1998-12-28

2000-07-25

Mai, Son

Static information storage and retrieval

Read/write circuit

Signals

365233, G11C 700

Patent

active

060943807

ABSTRACT:
A memory device with a data output buffer outputs the read data from the memory cell array without error and provides sufficent time in outputting the data. A memory device with a data output buffer means comprises a clock input buffer means for receiving an external clock and outputting an internal clock; and a delay means for delaying a specified time the internal clock outputted from the clock input buffer means; wherein the operation of the data output buffer means is controlled by the delayed internal clock outputted from the delay means.

REFERENCES:
patent: 5077693 (1991-12-01), Hardee et al.
patent: 5402389 (1995-03-01), Flannagan et al.
patent: 5566108 (1996-10-01), Kitamura
patent: 5608688 (1997-03-01), Park
patent: 5631866 (1997-05-01), Oka et al.
patent: 5648931 (1997-07-01), Obara
patent: 5663912 (1997-09-01), Yamauchi
patent: 5781499 (1998-07-01), Koshikawa
patent: 5955904 (1999-09-01), Kawasaki
patent: 5956290 (1999-09-01), Matsuzaki

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