Memory device which receives write masking information

Details Memory device which receives write masking information Memory device which receives write masking information

2005-06-28

2005-06-28

Nguyen, Hiep T. (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C711S167000

Reexamination Certificate

active

06912620

ABSTRACT:
A method is described for providing a memory with a serial sequence of write enable signals that are offset in time with respect to respective data received by a plurality of data inputs of the memory. A memory is also described with an array for data storage, a plurality of data input pins, and a separate pin for receiving either additional data or a serial sequence of write enable signals applicable to data received by the plurality of data input pins. The additional data that the separate pin can receive includes, for example, error detection and correction (EDC) information. A method is also described for multiplexing write enable information and error detection and correction information.

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