Memory device which can change control by chip select signal

Details Memory device which can change control by chip select signal Memory device which can change control by chip select signal

2003-02-13

2004-09-07

Mai, Son (Department: 2818)

Static information storage and retrieval

Read/write circuit

Signals

C365S189011

Reexamination Certificate

active

06788592

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2002-72725, filed on Mar. 15, 2002, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a memory device which can be selected by a chip select signal, and more particularly to a memory device which can change control by a chip select signal, and a memory device which can control by a plurality of chip select signals.
2. Description of the Related Art
A memory device such as a non-volatile semiconductor memory, including a flash memory, is normally selected by a chip select signal, writes data to a memory cell specified by an address signal, and reads data from the memory cell. For such a memory device, access is controlled by a memory control unit such as a CPU and memory controller (hereafter referred to as CPU). The CPU-which controls a plurality of memory devices selects one of the memory devices by a chip select signal, and supplies a predetermined number of bits of address signal to access a specific memory device. The address signal is commonly supplied to a plurality of memory devices under control.
Therefore a memory area which can be selected by a single chip select signal is restricted by the number of bits of the address signal. For example, if the bus width is 16 bits and the address signal is 22 bits, 64 MB of memory area can be accessed. Therefore a CPU having a 22 bit address signal can use a memory area exceeding 64 MB by using a plurality of chip select signals.
FIG. 1
is a diagram depicting the relationship of a conventional CPU and
2
memory devices. The CPU
10
is connected with 2 memory devices
12
and
14
in parallel by a bus which supplies 22 bit addresses A
0
-A
21
and a predetermined bit of data. And the CPU
10
outputs an address signal and supplies the chip select signals CS
1
or CS
2
to the corresponding memory devices. The memory device selected by the chip select signal is activated and executes the access operation to a memory cell corresponding to the address signals A
0
-A
21
.
FIG. 2
is a diagram depicting an example of the memory space of the CPU shown in FIG.
1
. In this example, the memory A has a 64 MB memory area, and the memory B has a 32 MB memory area (or memory area less than 32 MB). Since the address signal, A
0
to A
21
, has only 22 bits, the memory area which the CPU can control by the address signal is 64 MB. The CPU, on the other hand, can access 128 MB of memory space (memory area) by using 2 chip select signals, CS
1
and CS
2
, in addition to the address signal.
In the above example, however, the memory B has only a 32 MB or less memory area, so a 64 MB-96 MB area of memory space cannot be used. Such a situation occurs when the memory B is a memory which capacity is restricted, such as a high-speed RAM.
Therefore it is expected that the area of the memory A is expanded so that the memory space which cannot be used, 64 MB-96 MB area, can be used. For this, the second memory A having a 32 MB area, which is half of memory A, must be added. And it is necessary to supply the same chip select signal CS
2
to the second memory A and memory B, and to select the second memory A or memory B by the address signal.
However if the second memory A is added, the CPU controls a total of 3 memory devices. An increase in the number of memory devices in this way is inappropriate for applications where the requirement to save space for mounting devices is strict, such as a portable telephone and portable information terminal.
So an alternative is to use a memory device having 64 MB+32 MB, a total 96 MB area, or an area larger than this, such as 128 MB, as a large capacity memory instead of the memory A. Such a large capacity memory device, however, requires a 23 bit address signal, and cannot be controlled by a CPU which has only the 22 bit address terminal shown in FIG.
1
. As
FIG. 2
shows, this CPU
10
uses 2 chip select signals CS
1
, CS
2
in addition to the 22 bit address to control the 128 MB address area, but only 1 chip select signal can be supplied to a ordinary memory device. As a result, the large capacity memory device having a capacity which exceeds the memory area, which can be controlled by one chip select signal, cannot be directly connected to the CPU
10
.
SUMMARY OF THE INVENTION
With the foregoing in view, it is an object of the present invention to provide a memory device which can be directly connected to the memory control unit, even if the memory area exceeds the area which can be controlled by one chip select signal at the memory control unit side.
It is another object of the present invention to provide a memory device which can change between one control by a single chip select signal and another control by a plurality of chip select signals.
To achieve the above objects, the first aspect of the present invention is a memory device comprising an address terminal for inputting a plural bits of address signal, and a chip select terminal for inputting an external chip select signal, and an access mode controlling circuit which can switch a first control mode for controlling enable/disable of the memory device according to a plurality of external chip select signals and a predetermined address signal in the address signal to be input, and a second control mode for controlling enable/disable of the memory device according to a single external chip select signal.
If the memory device has a second memory area larger than a first memory area which can be controlled by a single chip select signal of the memory control unit, the memory device can be directly connected to the memory control unit by setting the access mode control circuit to the first control mode. In the first control mode, enable/disable of the memory device is controlled according to a plurality of external chip select signals and a predetermined address signal in the address signal to be input, so this memory device can be directly connected to the memory control unit, even if this memory device has an area exceeding the memory area which the memory control unit can control by a single chip select signal.
Also according to the above mentioned memory device, if the memory device has a memory-area less than the first memory area, which the memory control unit can control by a single chip set, then the access mode control circuit is set to the second control mode. Therefore the present invention can provide a memory device which can flexibly support various memory control units.
To achieve the above objects, the second aspect of the present invention is the memory device according to the first aspect, wherein in a first control mode, the access mode controlling circuit controls the memory device to be in enable status when one of the plurality of external chip select signals is in enable status, and controls the memory device in disable status according to the predetermined address signal, even if one external chip select signals is in enable status.
According to the second aspect of the present invention, when the memory control unit accesses a part of the memory area which can be controlled by the address signal and the plurality of chip select signals both to be supplied, this memory device is disabled so that access to an other memory device different from this memory device can be enabled. Therefore it is possible that a part of the memory device which the memory control unit can control is assigned to the other memory device, and the rest of the memory area is assigned to this memory device. As a result, the memory area which the memory control unit can control can be used effectively.
According to a preferable embodiment, in the first aspect of the present invention, if the memory chip in the memory device has the access mode control circuit which is switched to the first control mode, this memory chip is accommodated in a package having a plurality of chip select terminals, and if the

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