Memory device utilizing vertical nanotubes

Details Memory device utilizing vertical nanotubes Memory device utilizing vertical nanotubes

2006-02-14

2006-02-14

Tran, Mai-Huong (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Thin active physical layer which is

C257S012000, C257S027000, C257S030000, C257S315000, C257S324000, C438S962000

Reexamination Certificate

active

06998634

ABSTRACT:
A memory device using vertical nanotubes includes an array of first electrodes arranged in strips in a first direction, a dielectric layer deposited on the array of first electrodes, the dielectric layer having a plurality of holes arranged therein, an array of nanotubes for emitting electrons, the array of nanotubes contacting the array of first electrodes and vertically growing through the plurality of holes in the dielectric layer, an array of second electrodes arranged in strips in a second direction on the dielectric layer, the array of second electrodes contacting the array of nanotubes, wherein the second direction is perpendicular to the first direction, a memory cell positioned on the array of second electrodes for trapping electrons emitted from the array of nanotubes, and a gate electrode deposited on an upper surface of the memory cell for forming an electric field around the array of nanotubes.

REFERENCES:
patent: 6566704 (2003-05-01), Choi et al.
patent: 6707098 (2004-03-01), Hofmann et al.
patent: 2002-110977 (2002-04-01), None
patent: 2001-0017411 (2001-03-01), None

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