Memory device using one common bus line between address...

Details Memory device using one common bus line between address... Memory device using one common bus line between address...

1999-12-30

2001-05-08

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S191000

Reexamination Certificate

active

06229748

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device to reduce the number of address bus lines.
DESCRIPTION OF THE PRIOR ARTS
Generally, row address signals, which are input from an external circuit in order to select a word line, are first buffered in an address buffer to remove noises and to amplify signal level. Also, before being input into a row decoder, the row address signals are input into a row predecoder to select a word line.
FIG. 1
is a schematic diagram illustrating a conventional memory device having row address bus lines. In
FIG. 1
, the reference numeral
1
denotes an address buffer block,
2
a refresh counter,
3
a row predecoder,
4
a row decoder and
5
a memory array block, respectively. As shown in
FIG. 1
, the conventional memory device having the address buffer block
1
has two output terminals ADD and ADDB which are out of phase. The memory device receives the row address signals, selects a specific word line and performs write and read operations in each cell of the memory array block
5
. At this time, the memory device processing addresses signals A
0
to An requires n+1 address buffers and each address buffers are in need of two bus lines ADD and ADDB so that total numbers of the address bus lines to be required therein are 2 (n+1). Further, in a refresh mode, the refresh counter
2
to refresh the memory cells requires 2(n+1) bus lines.
The row predecoder
3
having 4-bit output data is shown in FIG.
2
. As shown in
FIG. 2
, the conventional row predecoder
3
requires
4
input lines including two input lines (address line (ADD) and address bar line (ADDB)) from the address buffers and further two input lines (refresh line (RCNT) and refresh bar line (RCNTB)). Furthermore, the conventional row predecoder
3
requires control lines to control external and internal address signals, i.e., external address catch signal EXT_AXT and internal (refresh) address catch signal INT_AXT and also requires many transistors connected to these lines.
As described above, since the conventional memory device requires two data lines per row address buffer, there are many problems in increasing the integration thereof. Particularly, since each address buffer is connected to two bus lines, the memory device may occupy the large chip area.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a highly integrated semiconductor memory device by reducing the number of bus lines of address buffers.
It is another object of the present invention to provide a highly integrated semiconductor memory device by reducing the number of transistors in a predecoder with the reduction of the number of bus lines of address buffers.
In accordance with an aspect of the present invention, there is provided a memory device comprising: a common data bus line; a plurality of address buffers coupled to the common data bus line for buffering external address signals; a refresh counter coupled to the common data bus line, including a buffer for providing refresh address signals; a first control means for selectively transferring the external address signals buffered in the address buffers to the common data bus line; and a second control means for selectively transferring the refresh address signals from the refresh counter to the common data bus line.
In accordance with another aspect of the present invention, there is provided a memory device comprising: a common data bus line; a plurality of address buffers and a plurality of a refresh counting buffers, wherein the address buffers receive external address signals and the refresh counting buffers receive refresh address signals and wherein the address buffers and the refresh counting buffers are coupled to the common data bus line; a first control means for selectively transferring address signals buffered in the address buffers to the common data bus line; a second control means for selectively transferring the refresh address signals buffered in the refresh counting buffer to the common data bus line; and a predecoder coupled to the common data bus line, wherein the predecoder includes four transistors receiving a predecoder catch signal and external or refresh address signals.


REFERENCES:
patent: 4580216 (1986-04-01), Bellay et al.

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