Memory device using multiple layer nano tube cell

Details Memory device using multiple layer nano tube cell Memory device using multiple layer nano tube cell

2007-10-16

2007-10-16

Lam, David (Department: 2827)

Static information storage and retrieval

Systems using particular element

Semiconductive

C365S149000, C365S230060

Reexamination Certificate

active

11058184

ABSTRACT:
A memory device features a multiple layer nano tube cell. In the memory device, a cross point cell array including a capacitor and a PNPN nano tube switch is effectively arranged to reduce the whole memory size. Also, in the memory device, the nano tube cell array including a capacitor and a PNPN nano tube switch which does not require an additional gate control signal is positioned on a circuit device region including a word line driving unit, a sense amplifier, a data bus, a main amplifier, a data buffer and an input/output port, and an interlayer insulating film is interposed between a cell array region and the circuit device region.

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