Memory device using block write mode, simultaneous column writes

Details Memory device using block write mode, simultaneous column writes Memory device using block write mode, simultaneous column writes

1996-11-26

1999-07-06

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

711104, 36523003, G06F 1200

Patent

active

059208830

ABSTRACT:
A column address selection circuit 1 is provided, which renders all column address signals (CSi), from a start address to a stop address designated by a column address signal (ADCd+ADCu), to be a selective level when a segment address selection signal (SASj) and a block write signal (BW) are at an active level. A segment address selection circuit 2 is provided, which renders all segment address selection signals (SASj), from the start address to the stop address designated by the column address signal (ADCu) of a superordinate side, to be a selection level to supply it to the column address selection circuit 1, when the block write signal (BW) is at the active level.

REFERENCES:
patent: 5134589 (1992-07-01), Hamano
patent: 5305278 (1994-04-01), Inoue
patent: 5422998 (1995-06-01), Margolin
patent: 5657287 (1997-08-01), McLaury et al.
"4M-Bit Dual Port Graphics Buffer 256K Words by 16 Bits", NEC, document No. IC-3585, Mar. 1995, pp. 27-29.

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