Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2001-07-20
2004-08-10
Padmanabhan, Mano (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S173000
Reexamination Certificate
active
06775742
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates, in general, to a memory device and to a method for providing the memory device, and more particularly to the memory device which stores data and directory information for at least one cache line thereon, and to the method which allocates sections of the memory device to store the directory information and the data thereon.
BACKGROUND OF THE INVENTION
In conventional computer systems, data is written into (and read from) a number of memory arrangements via known interfaces. With the current advances in the microprocessor controlling/accessing technology, it is now possible to utilize data busses which provide a large amount of data to the components of the existing computer systems. Thus, the current memory arrangements (which are either provided in or communicating with the known computer systems) are now capable of receiving, storing thereon and providing large amounts of data.
With the recent introduction of new processing arrangements (e.g., non-uniform memory access systems—“NUMA” systems), data caching schemes have been utilized to remove at least some of the data storage requirement from the memory arrangements. In addition, cache devices are now utilized in the computer systems or in a close vicinity thereto. In a typical NUMA computer system, each node of a number of interconnected nodes includes one or more processors and a local system memory. Such computer systems are identified as having a non-uniform memory access because each processor has a lower access latency with respect to the data stored in the system memory at its local node than with respect to the data stored in the system memory at a remote node. The NUMA systems can be further classified as either non-coherent or cache coherent, depending on whether or not the data coherency is maintained between the caches in different nodes.
Conventional large-scale multi-processors with coherent caches offer a flexible and powerful computing environment. Indeed, the coherent caches reduce the problems associated with data partitioning, and provide a better support for parallelizing compilers, standard operating systems, and multiprogramming so as to offer a more flexible and effective use of the machine. The research has progressed in this area to provide a Cache-Coherent Non-Uniform Memory Access (CC-NUMA) machine. The CC-NUMA machine has a distributed main memory, a scalable interconnection network, and directory-based cache coherence. The directory-based schemes provide cache coherence, consuming only a small fraction of the system bandwidth without requiring message broadcasts.
U.S. Pat. No. 5,535,116 (the entire disclosure is incorporated herein by reference) describes that a shared-memory computer system (such as the NUMA machine) can be formed from a plurality of tightly-coupled processing nodes. Each processing node has a data processor for executing software instructions, a main memory cache, a processor cache disposed between the data processor and the main memory cache, and a directory memory. The main memory cache caches to a global shared memory space organized in pages, each page having a plurality of respectively addressed data items. The directory memory centralizes the directory information for each data item assigned to the processing node. The computer also has a general interconnection network for coupling the processing nodes. The directory memory has a state memory for maintaining the current state of each data item assigned to the respective processing node. In addition, the directory memory has a pointer to a master node for each data item, the master node being the processing node which has a master copy of the data item.
A dynamic random access memory (“DRAM”) arrangement which includes a dual in-line memory module (“DIMM”) can be used in a directory based, distributed shared memory microprocessor computer system. One type of the DIMM (i.e., a high memory capacity DIMM) is described in U.S. Pat. No. 6,049,476, the entire disclosure of which is incorporated herein by reference. Such DIMM is used as the data memory to store the data, and as the state memory to store the state or directory information corresponding to at least one portion of the data. The above-described DIMM allows the data and the state information to be accessed independently.
However, the prior art does not disclose a memory system (including a portion or a partition which stores the directory information for each cache line), especially the memory system which can be used with the commercially available (or standard) DIMMs. In addition, it is preferable to utilize the above-mentioned memory system for various-sized DIMMs, and without the necessity to provide extensive changes to the configuration of the memory system. It is preferable to utilize an embedded or external software modules to configure the memory system for determining which portion of the memory system is configured to store the directory information provided for at least one cache line, and which portion is configured to store the data.
SUMMARY OF THE INVENTION
From the foregoing, it may be appreciated that a need has arisen for a memory system which includes a portion/partition thereof that is configured to store directory information for each respective cache line, and another portion that is configured to store data. In accordance with the present invention, a memory device and method are provided to fulfill such need.
According to an embodiment of the present invention, there is provided a memory device and method which provide at least one memory segment in the memory device. The memory segment includes at least one first portion configured to store the data. The memory segment also includes at least one second portion which is associated with the first portion and configured to store the directory information provided for at least one cache line.
In another embodiment of the present invention, a plurality of memory segments (e.g., four memory segments) are provided, and each of the memory segments includes the corresponding first portion and the corresponding second portion.
According to yet another embodiment of the present invention, the memory segment is capable of providing the data and the directory information simultaneously.
In a further embodiment of the present invention, the second portion is provided at a predetermined address of the memory segment, the predetermined address being provided in a top-most section of the memory segment.
In another embodiment of the present invention, the memory segment is coupled to a further arrangement (e.g., a chip) via a single communication line. In response to a request from the further arrangement, the memory segment provides the data and the directory information to the further arrangement via the single communication line.
According to yet another embodiment of the present invention, the second portion has a size approximately {fraction (1/32)} of a size of the memory segment. In addition, at least two of the memory segments may differ in size.
In a further embodiment of the present invention, the directory information is cached, and the memory segment may be arranged in a single memory unit. The memory segment can also be provided on a commercially available (e.g., standard) dual in-line memory module (DIMM).
According to still another embodiment of the present invention, there are two sets of the memory segments. A first set of the memory segments is connected to a first bus, and a second set of the memory segments is connected to a second bus.
Other technical advantages may be readily apparent to those skilled in the art from the following figures, description, and claims.
REFERENCES:
patent: 5835928 (1998-11-01), Auslander et al.
patent: 5905996 (1999-05-01), Pawlowski
patent: 6049476 (2000-04-01), Laudon et al.
patent: 6473833 (2002-10-01), Arimilli et al.
patent: 6560681 (2003-05-01), Wilson et al.
International Search Report in International Application No. PCT/US 01/23109, dated Oct. 30, 2001, 6 pages.
Huffman William A.
Kuskin Jeffrey S.
Baker Paul
Baker & Botts L.L.P.
Padmanabhan Mano
Silicon Graphics Inc.
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