Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Correction for skew – phase – or rate
Reexamination Certificate
2008-07-08
2008-07-08
Lee, Thomas (Department: 2115)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Correction for skew, phase, or rate
C711S105000
Reexamination Certificate
active
07398413
ABSTRACT:
A memory system includes a memory controller and a memory component coupled to each other. The memory controller includes an interface to receive a first signal and a second signal from the memory component, wherein the first signal comprises a first symbol and the second signal comprises a second symbol. A first circuit of the memory controller receives the first signal by sampling the first symbol using a first timing offset relative to a reference clock signal, and a second circuit of the memory controller receives the second signal by sampling the second symbol using a second timing offset relative to the reference clock signal. The first timing offset is independent of the second timing offset.
REFERENCES:
patent: 3753232 (1973-08-01), Sporer
patent: 4893318 (1990-01-01), Potash et al.
patent: 5077759 (1991-12-01), Nakahara
patent: 5097489 (1992-03-01), Tucci
patent: 5268639 (1993-12-01), Gasbarro et al.
patent: 5325053 (1994-06-01), Gasbarro et al.
patent: 5357195 (1994-10-01), Gasbarro et al.
patent: 5485490 (1996-01-01), Leung et al.
patent: 5554945 (1996-09-01), Lee et al.
patent: 5577236 (1996-11-01), Johnson et al.
patent: 5579352 (1996-11-01), Llewellyn
patent: 5589788 (1996-12-01), Goto
patent: 5598540 (1997-01-01), Krueger
patent: 5614855 (1997-03-01), Lee et al.
patent: 5615358 (1997-03-01), Vogley
patent: 5657481 (1997-08-01), Farmwald et al.
patent: 5671231 (1997-09-01), Cooper
patent: 5684421 (1997-11-01), Chapman et al.
patent: 5805603 (1998-09-01), Araki et al.
patent: 5828568 (1998-10-01), Sunakawa et al.
patent: 5831929 (1998-11-01), Manning
patent: 5872736 (1999-02-01), Keeth
patent: 5892981 (1999-04-01), Wiggers
patent: 5910920 (1999-06-01), Keeth
patent: 5917760 (1999-06-01), Millar
patent: 5926034 (1999-07-01), Seyyedy
patent: 5940608 (1999-08-01), Manning
patent: 5940609 (1999-08-01), Harrison
patent: 5946244 (1999-08-01), Manning
patent: 5953284 (1999-09-01), Baker et al.
patent: 5963502 (1999-10-01), Watanabe et al.
patent: 5986955 (1999-11-01), Sick et al.
patent: 6000022 (1999-12-01), Manning
patent: 6006339 (1999-12-01), McClure
patent: 6011732 (2000-01-01), Harrison et al.
patent: 6016282 (2000-01-01), Keeth
patent: 6026050 (2000-02-01), Baker et al.
patent: 6029250 (2000-02-01), Keeth
patent: 6047346 (2000-04-01), Lau et al.
patent: 6078623 (2000-06-01), Isobe et al.
patent: 6101152 (2000-08-01), Farmwald et al.
patent: 6125157 (2000-09-01), Donnelly et al.
patent: 6128244 (2000-10-01), Thompson et al.
patent: 6131149 (2000-10-01), Lu et al.
patent: 6154821 (2000-11-01), Barth et al.
patent: 6160423 (2000-12-01), Haq
patent: 6169434 (2001-01-01), Portmann
patent: 6240128 (2001-05-01), Banerjea et al.
patent: 6247138 (2001-06-01), Tamura et al.
patent: 6262921 (2001-07-01), Manning
patent: 6279073 (2001-08-01), McCracken et al.
patent: 6282210 (2001-08-01), Rapport et al.
patent: 6292903 (2001-09-01), Coteus et al.
patent: RE37452 (2001-11-01), Donnelly et al.
patent: 6316980 (2001-11-01), Vogt et al.
patent: 6330683 (2001-12-01), Jeddeloh
patent: 6359815 (2002-03-01), Sato et al.
patent: 6362995 (2002-03-01), Moon
patent: 6369627 (2002-04-01), Tomita
patent: 6373293 (2002-04-01), Best
patent: 6374360 (2002-04-01), Keeth et al.
patent: 6378079 (2002-04-01), Mullarkey
patent: 6397042 (2002-05-01), Prentice et al.
patent: 6498522 (2002-12-01), Ikeda et al.
patent: 6510503 (2003-01-01), Gillingham et al.
patent: 6532179 (2003-03-01), Yagishita
patent: 6553472 (2003-04-01), Yang et al.
patent: 6587525 (2003-07-01), Jeong et al.
patent: 6608829 (2003-08-01), Johnson
patent: 6611905 (2003-08-01), Grundon et al.
patent: 6643787 (2003-11-01), Zerbe et al.
patent: 6646953 (2003-11-01), Stark
patent: 6675272 (2004-01-01), Ware et al.
patent: 6724846 (2004-04-01), Lo
patent: 6779096 (2004-08-01), Cornelius et al.
patent: 6804764 (2004-10-01), LaBerge et al.
patent: 6807614 (2004-10-01), Chung
patent: 6928571 (2005-08-01), Bonella et al.
patent: 6949958 (2005-09-01), Zerbe et al.
patent: 6970988 (2005-11-01), Chung
patent: 7010077 (2006-03-01), Dunlop et al.
patent: 7076745 (2006-07-01), Togo
patent: 7100066 (2006-08-01), Jeong
patent: 7159092 (2007-01-01), Johnson et al.
patent: 7224595 (2007-05-01), Dreps et al.
patent: 2001/0021141 (2001-09-01), Ikeda et al.
patent: 2001/0026479 (2001-10-01), Yagishita
patent: 2001/0047450 (2001-11-01), Gillingham et al.
patent: 2002/0075748 (2002-06-01), Benzinger et al.
patent: 2002/0174311 (2002-11-01), Ware et al.
patent: 2002/0191475 (2002-12-01), Lee et al.
patent: 2002/0196885 (2002-12-01), Kim et al.
patent: 2003/0212930 (2003-11-01), Aung et al.
patent: 2355571 (2001-04-01), None
patent: WO 01/85884 (2001-11-01), None
Abdelrahman, Accessed Jul. 3, 2002, “Scheduling of wavefront parallelism on scalable shared-memory multiprocessors,” IEEE Xplore, http://ieeexplore.ieee.org.
Hammamoto et al., 1998, 400-MHz random column operating SDRAM techniques with self-skew compensation, IEEE Journal of Solid-State Circuits, 33:770-778.
Sidiropoulos, 1997, A 700-Mb/pin CMOS signaling interface using current integrated receivers, IEEE Journal of Solid-State Circuits, 32:681-690.
Yoshimura, 1996, “A 622-Mb/s bit/frame synchronizer for high-speed backplane data communication,” IEEE Journal of Solid-State Circuits, 31:1063-1066.
Wang et al., 2001, “A 500-Mb/s quadruple data rate SDRAM interface using a skew cancellation technique,” IEEE Journal of Solid-State Circuits, 36:648-657.
Sato et al., 1999, “A 5-Gbyte/s data-transfer scheme with bit-to-bit skew control for synchronous DRAM,” IEEE Journal of Solid-State Circuits, 34:653-660.
Maheshwari, 1999, “Optimizing large multiphase level-clocked circuits,” IEEE Journal of Solid-State Circuits, 18:1249-1264.
Yeung et al., 2000 “A 2.4 Gb/s/pin simultaneous bidirectional parallel link with per-pin skew compensation,” IEEE Journal of Solid-State Circuits, 35:1619-1627.
1999 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, ISSCC, Feb. 1995, John H. Wuorinen, Publisher.
1998, “High-performance parallel interface-framing protocol (HIPPI-FP)”, American National Standard for Information Technology, 210-1998.
Sato et al., 1998 “5 Gbyte/s data transfer scheme with bit-to-bit skew control for synchronous DRAM,” 1998 Symposium on VLSI Circuits—Digest of Technical Papers, Jun. 11-13, 1998, Honolulu, Hawaii.
1998, “Media access control (MAC) parameters, physical layer, repeater and management parameters for 1000 Mb/s operation—supplement to carrier sense multiple access with collision detection (CSMA/CD) access method & physical layer specifications,” IEEE Draft P802.3z/D5.0—LAN MAN Standards Committee of the IEEE Computer Society.
PCT International Search Report, International Application No. PCT/US2002/33707, International Filing Date Oct. 22, 2002.
Chang et al., “A 2 Gb/s/pin asymmetric serial link,” Dept of Electrical Engineering, Stanford Univ., Serial Link:1-24.
Chang et al., “A 2 Gb/s asymmetric serial link for high-bandwidth packet switches,” Computer System Laboratory, Stanford Univ., pp. 1-9.
Chang et al., “A 2 Gb/s/pin CMOS asymmetric serial link,” Computer System Laboratory, Stanford Univ.
McKeown et al., The Tiny Tera: A Packet Switch Core, Depts. of Electrical Engineering and Computer Science, Stanford Univ.
Cecchi, D. et al., “FP 20.2: A 1GB/S 8-C1 Link in 0.8μm BICMOS,” IEEE International Solid-State Circuits Conference, Digest of Technical Papers, Feb. 1995, pp. 326-327.
Gillingham, P., “SLDRAM Architectural and Functional Overview,” 1997 SLDRAM Consortium, Aug. 29, 1997, pp. 1-14.
Koo, Y., et al., A 4-400MHz Jitter-Suppressed Delay-Locked Loop with Frequency Division Method, 6thInt'l Conference on VLSI and CAD, Seoul, South Korea, Oct. 26-27, 1999, pp. 339-341.
Kushiyama, N., et al., “A 500-Megabyte/s Data-Rate 4.5M DRAM,”IEEE Journal of Solid State Circuits, vol. 28, No. 4, Apr. 1993, pp. 490-498.
Park, J., et
Hampel Craig E.
Perego Richard E.
Sidiropoulos Stefanos S.
Tsern Ely K.
Ware Fredrick A.
Lee Thomas
Morgan & Lewis & Bockius, LLP
Rambus Inc.
Tran Vincent T
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