Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
2005-08-24
2009-11-17
Thai, Tuan V (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C711S163000, C711S169000, C713S500000, C713S501000, C713S600000, C713S400000
Reexamination Certificate
active
07620788
ABSTRACT:
A sequence state matrix has a plurality of time slots for storing a plurality of memory device signals. The memory device signals are loaded into the matrix by a sequencer load unit, which loads the memory device signals at locations in the matrix corresponding to the times that the signals will be coupled to a memory device. The sequencer load unit loads the signals into the matrix at a rate corresponding to a frequency of a system clock signal controlling the operation of the electronic system. A first in, first out (“FIFO”) buffer receives the memory device signals from the sequence state matrix at a rate corresponding to the frequency of the system clock signal. A command selector transfers the memory device signals from the FIFO buffer to the memory device at a rate corresponding to the frequency of a memory clock signal controlling the operation of the memory device.
REFERENCES:
patent: 4245303 (1981-01-01), Durvasula et al.
patent: 5155809 (1992-10-01), Baker et al.
patent: 5448715 (1995-09-01), Lelm et al.
patent: 5471587 (1995-11-01), Fernando
patent: 5487092 (1996-01-01), Finney et al.
patent: 5600824 (1997-02-01), Williams et al.
patent: 5915107 (1999-06-01), Maley et al.
patent: 5923193 (1999-07-01), Bloch et al.
patent: 5923858 (1999-07-01), Kanekal
patent: 6000022 (1999-12-01), Manning
patent: 6006340 (1999-12-01), O'Connell
patent: 6016549 (2000-01-01), Matsushiba et al.
patent: 6112307 (2000-08-01), Ajanovic et al.
patent: 6128749 (2000-10-01), McDonnell et al.
patent: 6134638 (2000-10-01), Olarig et al.
patent: 6202119 (2001-03-01), Manning
patent: 6279077 (2001-08-01), Nasserbakht et al.
patent: 6279090 (2001-08-01), Manning
patent: 6363076 (2002-03-01), Allison et al.
patent: 6370600 (2002-04-01), Hughes et al.
patent: 6389529 (2002-05-01), Arimilli et al.
patent: 6414903 (2002-07-01), Keeth et al.
patent: 6434684 (2002-08-01), Manning
patent: 6449703 (2002-09-01), Jeddeloh
patent: 6526469 (2003-02-01), Drehmel et al.
patent: 6542569 (2003-04-01), Manning
patent: 6542980 (2003-04-01), Chapelle et al.
patent: 6546451 (2003-04-01), Venkataraman et al.
patent: 6590901 (2003-07-01), Jones
patent: 6594713 (2003-07-01), Fuoco et al.
patent: 6622228 (2003-09-01), Jeddeloh
patent: 6718449 (2004-04-01), Phi
patent: 6775755 (2004-08-01), Manning
patent: 2003/0169757 (2003-09-01), LaVigne et al.
patent: 2007/0086480 (2007-04-01), Elzur
Microsoft Dictionary, 1999, Microsoft Press, Fourth Edition, pp. 159 and 399.
Dorsey & Whitney LLP
Micro)n Technology, Inc.
Rojas Midys
Thai Tuan V
LandOfFree
Memory device sequencer and method supporting multiple... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Memory device sequencer and method supporting multiple..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory device sequencer and method supporting multiple... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4107333