Memory device sequencer and method supporting multiple...

Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing

Reexamination Certificate

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Details

C711S169000, C713S400000, C713S500000, C713S501000, C713S600000

Reexamination Certificate

active

06983354

ABSTRACT:
A sequence state matrix has a plurality of time slots for storing a plurality of memory device signals. The memory device signals are loaded into the matrix by a sequencer load unit, which loads the memory device signals at locations in the matrix corresponding to the times that the signals will be coupled to a memory device. The sequencer load unit loads the signals into the matrix at a rate corresponding to a frequency of a system clock signal controlling the operation of the electronic system. A first in, first out (“FIFO”) buffer receives the memory device signals from the sequence state matrix at a rate corresponding to the frequency of the system clock signal. A command selector transfers the memory device signals from the FIFO buffer to the memory device at a rate corresponding to the frequency of a memory clock signal controlling the operation of the memory device.

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