Memory device, memory system and method of...

Details Memory device, memory system and method of... Memory device, memory system and method of...

2008-04-29

2008-04-29

Ho, Hoai V. (Department: 2827)

Static information storage and retrieval

Addressing

Sync/clocking

C365S149000, C365S189050

Reexamination Certificate

active

07366052

ABSTRACT:
A memory device includes a memory cell array, a row decoding section, a K-bit prefetch section and an output buffer section. The row decoding section decodes a row address in response to a first clock, to activate one of the word lines corresponding to the decoded row address. The K-bit prefetch section decodes a column address in response to a second clock and prefetches K data from K memory cells connected to the activated word line and corresponds to the decoded column address, in response to a second clock, where a frequency of the second clock is 1/M of that of the first clock. The output buffer section outputs the K prefetched data as a data stream in response to a third clock. Therefore, a burden from the physical limit of the access speed may be alleviated when the data I/O speed is increased.

REFERENCES:
patent: 6260128 (2001-07-01), Ohshima et al.
patent: 6978389 (2005-12-01), Jahnke

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