Memory device including parallel test circuit

Details Memory device including parallel test circuit Memory device including parallel test circuit

2006-10-24

2006-10-24

Phan, Trong (Department: 2827)

Static information storage and retrieval

Read/write circuit

Testing

C365S233100

Reexamination Certificate

active

07126865

ABSTRACT:
A memory device including a parallel test circuit can overcome a channel deficiency phenomenon of test equipment by reducing the number of input/output pads. The memory device including a parallel test circuit comprises a burst length regulating block, a parallel test block, an output block and a plurality of input/output pads. The burst length regulating block sets a second burst length at a test mode which is longer than a first burst length at a normal mode. The parallel test block compresses data and tests the compressed data by a repair unit. The output block sequentially outputs data outputted from at least two or more parallel test blocks depending on the second burst length. The plurality of input/output pads externally output data outputted from the output block.

REFERENCES:
patent: 6381715 (2002-04-01), Bauman et al.
patent: 6529428 (2003-03-01), Oh
patent: 6606274 (2003-08-01), Ooishi et al.
patent: 6917563 (2005-07-01), Lindstedt et al.
patent: 10-1996-0037470 (1999-09-01), None

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