Memory device including a memory array having a combination of t

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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257301, 257303, 257306, 257307, 257905, H01L 27108

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active

059427779

ABSTRACT:
A memory device is presented including a memory array having both trench capacitor and stacked capacitor DRAM cells. The trench and stacked capacitor DRAM cells are arranged in a configuration which achieves increased cell density while providing adequate electrical isolation between cells. The increased density of the memory array results in an increase in operational performance and a decrease in cost on a per storage bit basis. The memory array includes electrically conductive bit and word lines. The bit lines are arranged in vertical columns. The trench capacitor DRAM cells are arranged in pairs and aligned along the bit lines. Each pair of trench capacitor DRAM cells shares a common electrical contact to the bit line to which the pair is aligned. Capacitors of the stacked capacitor DRAM cells may be formed above the bit lines. A portion of the word lines are arranged in horizontal rows substantially orthogonal to the bit lines, and the remainder of the word lines are arranged in vertical columns and interleaved with the bit lines. The stacked capacitor DRAM cells are formed between the word lines arranged in rows, and are organized in pairs. Each pair of stacked capacitor DRAM cells shares a common electrical contact to an adjacent bit line. Each of the word lines arranged in rows forms a gate electrode of trench capacitor DRAM cells, and each of the word lines arranged in columns forms the gate electrode of stacked capacitor DRAM cells.

REFERENCES:
patent: 5057888 (1991-10-01), Fazan et al.
patent: 5124765 (1992-06-01), Kim et al.
patent: 5363326 (1994-11-01), Nakajima
patent: 5770874 (1998-06-01), Egawa

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