Memory device in which memory cells having complementary...

Details Memory device in which memory cells having complementary... Memory device in which memory cells having complementary...

2005-11-01

2005-11-01

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Read/write circuit

For complementary information

C365S063000, C365S205000

Reexamination Certificate

active

06961271

ABSTRACT:
A memory cell array block has unit memory cells comprised of pairs of memory cells, each of have a memory cell and a complementary memory cell. A second unit memory cell is interleaved with the first unit memory cell, a fourth unit memory cell is interleaved with a third unit memory cell. First and second sense amplifiers are disposed over and under the array block, respectively. The first switch connects bitlines coupled to the first unit memory cell with the first sense amplifier and connects bitlines coupled to the second unit memory cell with the second sense amplifier. The second switch connects bitlines coupled to the third unit memory cell with the first sense amplifier and connects bitlines coupled to the fourth unit memory cell with the second sense amplifier. A selected unit memory cell is selectively connected with a sense amplifier, decreasing the number of sense amplifiers.

REFERENCES:
patent: 6125071 (2000-09-01), Kohno et al.
patent: 6344990 (2002-02-01), Matsumiya et al.
patent: 6608772 (2003-08-01), Ooishi

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