Static information storage and retrieval – Read/write circuit – Testing
Patent
1999-04-12
2000-06-27
Le, Vu A.
Static information storage and retrieval
Read/write circuit
Testing
36518902, 36523002, G11C 700
Patent
active
060814675
ABSTRACT:
A memory device having two or more memory arrays and a testpath operatively connected to one of the memory arrays and not operatively connected to another of the memory arrays at substantially the same time. The memory device may include multiplexers and sense amplifiers to connect the datapath to the memory arrays. The memory device may also include a datapath connected to two or more memory arrays at the same time through multiplexers and sense amplifiers. The memory array may also be embodied as a memory system, including a processor, control logic, and the memory device. A method of operating a testpath of the memory device includes generating control signals to operatively connect the testpath to one of the memory arrays, and not to connect the testpath to another of the memory arrays at substantially the same time.
REFERENCES:
patent: 5726994 (1998-03-01), Matsuura et al.
patent: 5740098 (1998-04-01), Adams et al.
patent: 5848017 (1998-12-01), Bissey
Le Vu A.
Micro)n Technology, Inc.
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