Static information storage and retrieval – Read/write circuit – Simultaneous operations
Reexamination Certificate
2005-05-03
2005-05-03
Nguyen, Van Thu (Department: 2824)
Static information storage and retrieval
Read/write circuit
Simultaneous operations
C365S189070, C365S222000
Reexamination Certificate
active
06888761
ABSTRACT:
A system-on-chip (SOC) device or a random access memory (RAM) chip includes a RAM block. The RAM block includes memory cells, each of which has three transistors. Each memory cell is coupled to both a read bit line and a write bit line. A transparent continuous refresh mechanism has been implemented to read the content of a memory cell and re-write it back to the memory cell without disturbing the access (read/write) cycle, making refresh operations transparent to the system level. The continuous refresh mechanism includes a collision detection mechanism to prevent writing and reading the same memory cell at the same time.
REFERENCES:
patent: 3599180 (1971-08-01), Rubinstein et al.
patent: 3699544 (1972-10-01), Joynson et al.
patent: 4847809 (1989-07-01), Suzuki
patent: 5007022 (1991-04-01), Leigh
patent: 5596545 (1997-01-01), Lin
patent: 5691949 (1997-11-01), Hively et al.
patent: 5808932 (1998-09-01), Irrinki et al.
patent: RE36180 (1999-04-01), Lim
patent: 5963497 (1999-10-01), Holland
patent: 5995433 (1999-11-01), Liao
patent: 5999474 (1999-12-01), Leung et al.
patent: 6134169 (2000-10-01), Tanaka
patent: 6233193 (2001-05-01), Holland et al.
Afghahi Cyrus
Issa Sami
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