Memory device having row decoder

Details Memory device having row decoder Memory device having row decoder

1999-06-29

2000-08-29

Nelms, David

Static information storage and retrieval

Read/write circuit

Signals

365193, 365233, G11C 700

Patent

active

061117951

ABSTRACT:
On one hand, a row address is provided via a buffer gate to a row address register 11, and its output is provided via a complementary signal generation circuit 15 and a predecoder 16 to a word decoder 17A. On the other hand, in response to an issuance of an activate command a control signal AS1 is provided via a delay circuit 14 to the clock input CK of the row address register 11 as a strobe signal AS2, and AS2 is provided, to reduce timing margin, via a delay circuit 20A to the strobe signal input of the predecoder 16 as a strobe signal S2. S2 is provided via a delay circuit 20B to the strobe signal input of the word decoder 17A having RS flip-flops 2301 to 2332 or latch circuits. Each of the latch circuits consists of a NOR gate having a set input and a reset input and another NOR gate having an input coupled to receive the output of the former NOR gate and another set input to receive a multiple selection signal which is common for all the latch circuits in word decoders.

REFERENCES:
patent: 5581512 (1996-12-01), Kitamura
patent: 5844857 (1998-12-01), Son et al.

Affiliated with

Also associated with

Rating

Memory device having row decoder does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory device having row decoder, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory device having row decoder will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1255680