Static information storage and retrieval – Read/write circuit – Differential sensing
Reexamination Certificate
2002-10-31
2004-11-16
Elms, Richard (Department: 2824)
Static information storage and retrieval
Read/write circuit
Differential sensing
C365S185200, C365S185260, C365S185290, C365S226000
Reexamination Certificate
active
06819615
ABSTRACT:
TECHNICAL FIELD
The present invention generally pertains to the field of memory arrays. More particularly, embodiments of the present invention are related to a memory array reference cell having an added series resistance to improve reliability in reading cells in the memory array.
BACKGROUND ART
Non-volatile, reprogrammable memory devices such as flash memory are highly desirable and have many applications from storing a computer system's BIOS to functioning as a memory for devices such as digital cameras. Typically, such memory devices may be reprogrammed hundreds of thousands of times and may be programmed or erased in blocks of, for example, hundreds or thousands of bits. Such devices may operate by storing a charge in a memory cell. For example, a typical flash memory cell may be programmed to hold a charge in a floating gate region of a transistor.
By storing a charge in the floating gate, the memory cell transistor's threshold voltage (V
t
) is increased relative to the case when the gate holds no charge. This charge may be detected by applying voltages to the transistor and sensing a drain to source current. For example, a first voltage may be applied between the transistor's gate and source, while applying a second voltage between its drain and source. The applied gate to source voltage is between the programmed V
t
and the erased V
t
. In this fashion, if the transistor produces a significant current (I
DS
), it is assumed that the V
t
is low and the transistor is erased. If the transistor produces very little or no current, it is assumed that the V
t
is high and the transistor is programmed.
In order to determined if the current is ‘high’ or ‘low’, the current is typically compared to a reference current that is produced by a reference memory cell that has been fabricated to be nearly identical to the cells in the memory core. Thus, with the same applied voltages it should produce the same l
DS
.
FIG. 1
shows an I
DS
versus V
GS
graph
100
illustrating two curves, an erased curve
101
referring to a transistor with a low threshold voltage (V
ta
) and a programmed curve
102
referring to a transistor with a high threshold voltage V
tp
. If a read voltage (V
read
) is applied between the respective transistor's gates and ground (along with a suitable drain to source voltage), then the drain to source current (I
read
) may be found from the y-axis. If the transistor was programmed, I
read
is expected to be very low or zero. If the transistor was erased, I
read
is expected to be near the value seen on the y-axis.
However, the fabrication process cannot produce every transistor to be exactly the same. Therefore, the programmed and erased curves for each transistor will not be identical. Consequently, the margin between the two curves will not be as great as the ideal case shown in FIG.
1
. It is desirable to keep the margins as high as possible for reliable reading of the memory cells.
As one example of the importance of keeping read margins high, consider multi-level flash. These technologies store one of several different amounts of charge in the floating gate to create one of several different V
t
. The reliability of such multi-level flash is hard to achieve because the margin between one voltage threshold level and the next has to be small to establish multi-levels. To widen the voltage threshold window, multi-level flash may operate at higher voltages than other memories. However, higher operating voltages cause other problems, such as oxide breakdown. Thus, alternative means of increasing margins are sought for this and other floating gate memories.
Thus, a need has arisen for a high-density non-volatile memory array. A still further need exists for a high-density non-volatile memory array having high reliability. An even further need exists for a non-volatile memory array that may be fabricated with existing semiconductor processing techniques without considerable revamping of the fabrication process.
SUMMARY
Embodiments of the present invention provide a high-density non-volatile memory array. Embodiments of the present invention provide for a high-density non-volatile memory array having high reliability. Embodiments of the present invention provide for a non-volatile memory array that may be fabricated with existing semiconductor processing techniques without considerable revamping of the fabrication process.
A reference array having a reference cell with an added series resistance to improve reliability in reading cells in an associated memory array is disclosed. The reference array comprises a plurality of transistors, one of the transistors serving as a reference cell transistor. The plurality of transistors are fabricated with similar dimensions and characteristics as a transistors in the associated memory array. The reference cell transistor is for producing a reference current for reading memory cells in the associated memory array by comparing the reference current to a current produced by individual transistors of the memory cells. The reference cell transistor is coupled in series with a resistive element such that the reference current flows therethrough to reduce a voltage between a gate and a source of the reference cell. This bends the I
ds
versus V
gate
curve of the reference cell downward and compensates for irregularities in the resistance seen in series with the memory cell transistors. In this fashion, the margin when reading memory cells is improved and the reference current is more reliable.
The resistive element may be external to a region having the memory array and reference cell. For example, it may comprise a polysilicon region in area peripheral to the memory array. Alternatively, the resistive element may be internal to region with the memory array and reference cell. For example, it may be formed by extending the source region of the reference cell.
These and other advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiments which are illustrated in the various drawing figures.
REFERENCES:
patent: 5537358 (1996-07-01), Fong
patent: 5898617 (1999-04-01), Bushey et al.
patent: 2003/0043621 (2003-03-01), Wong
Fastow Richard M.
Leung Wing Han
Wang John
Advanced Micro Device Inc.
Elms Richard
Luu Pho M.
Wagner , Murabito & Hao LLP
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