Memory device having potential control for increasing the operat

Details Memory device having potential control for increasing the operat Memory device having potential control for increasing the operat

1997-10-10

2000-12-05

Le, Vu A.

Static information storage and retrieval

Read/write circuit

Flip-flop used for sensing

365207, 365208, G11C 700

Patent

active

061575860

ABSTRACT:
A sense amplifier including a pair of NMOS transistors connected in series between a pair of bit lines differential-amplifies the potential difference between the pair of bit lines by reducing the source potentials of the NMOS transistors to ground potential. An NMOS transistor is activated for a predetermined time after initiation of a differential amplification by the sense amplifier, whereby the source potentials of the NMOS transistors are controlled so as to attain a potential lower than the ground potential during that predetermined time. As a result, the operation margin of the NMOS transistors is increased during the predetermined time period.

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Tachibana et al., "Design of Overdrive Sense Amplifier for High-Speed DRAM," IEEE J. Solid-State Circuits, Nov. 1991, pp. 5-153.
Horiguchi et al., "A Tunable CMOS-DRAM Voltage Limiter with Stabilized Feedback Amplifier," 1990, pp. 75-76.
Okamura et al., "Decoded-Source Sense Amplifier for High-Density DRAM's", IEEE Journal of Solid-State Circuits, vol. 25, No. 1 (Feb. 1990), pp. 18-23.

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