Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
2000-08-21
2003-11-11
Sparks, Donald (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C711S158000, C711S159000, C711S163000, C711S169000
Reexamination Certificate
active
06647470
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to memory devices, and more particularly to a memory device that determines if write data should be posted on a per command basis for improving system bus efficiency.
2. Description of the Related Art
An increasing number of electronic equipment and electronic-based systems requires some form of high-speed memory devices for storing and retrieving information (or “data”). While the types of such memory devices vary widely, semiconductor memory devices are most commonly used in memory applications requiring implementation in a relatively small area. Within this class of semiconductor memory devices, the DRAM (Dynamic Random Access Memory) is one of the more commonly used types.
Many of the operations performed by the central processing unit (CPU) of these systems are memory accesses on the memory arrays of the system. The term access typically refers to reading data from or writing data to selected memory cells.
FIG. 1A
illustrates, in block diagram form, a portion of the components for accessing a conventional memory device. Array
10
consists of a plurality of memory cells arranged in rows and columns, into which and from which data can be written and read. Data is provided on the data inputs/outputs DQs
22
from a system bus (not shown) and input data is supplied to the data input registers
20
via bus
26
. The input data is latched by the write latch
16
, and placed on the bus
24
for input to the I/O gates
12
. The I/O gates
12
then write the data via bus
28
to the array
10
. Similarly, when data is to be read from the array
10
, the data is provided to the I/O gates
12
by bus
28
and input to the read latch
14
via bus
24
. The latched data is then driven by drivers
18
and output to a system bus (not shown) on the DQs
22
via bus
26
.
There are some shortcomings, however, with the conventional system for accessing memory arrays. For example, conventional access systems typically have slow write to read cycle times, i.e., the time required to perform a data write and then a data read. This is caused by the delay required for the I/O gates
12
to write the data into the array
10
before data can be provided from the array
10
to the I/O gates
12
during the read.
As processor speeds continue to increase, increased memory access speeds are becoming more important. There have been attempts to decrease the write to read cycle time by “posting” the data to be written into the array. Posting refers to placing the data to be written into the array in a data-buffer
30
as shown in
FIG. 1B
, and delaying the writing of the data to the memory array until the controller determines an available time when the I/O gates are not being used for a read operation, such as for example a subsequent write command. For example, the data in the buffer
30
will be put into the write latch
16
and subsequently into the array
10
through I/O gates
12
when a new write command is issued, and new data (from the new write command) is being input to the buffer
30
. However, posting every write data will always delay the write access to the memory array, thereby reducing the system efficiency. Additionally, when a read command follows several write commands, if the data in the buffer
30
is not written into the array
10
before the read command is executed, there is the risk of the data in the buffer
30
becoming corrupted. Accordingly, there will still be a delay between the last write command before a read command can be executed to ensure the data is not corrupted.
Accordingly, it is desirous to increase memory access speed by decreasing the write to read cycle time, without reducing the system efficiency by always delaying write commands.
SUMMARY OF THE INVENTION
The present invention alleviates some of the problems of the prior art and provides a unique system and method for decreasing the memory access time by determining if data will be written directly to the array or be posted through a data buffer on a per command basis, thereby optimizing the system efficiency.
In accordance with the present invention, a memory controller determines if data to be written to a memory array, such as a DRAM array, is either written directly to the array or posted through a data buffer on a per command basis. If the controller determines that a write command is going to be followed by another write command, the data associated with the first write command will be written directly into the memory array without posting the data in the buffer. If the controller determines that a write command will be followed by a read command, the data associated with the write command will be posted in the data buffer, allowing the read command to occur with minimal delay, and the posted data will then be written into the array when the internal I/O lines are no longer being used to execute the read command. By determining whether or not to post the data on a per command basis, the memory controller has greater flexibility for improved data throughput.
These and other advantages and features of the invention will become more readily apparent from the following detailed description of the invention which is provided in connection with the accompanying drawings.
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Dickstein , Shapiro, Morin & Oshinsky, LLP
Micro)n Technology, Inc.
Peugh Brian R.
Sparks Donald
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