Memory device having pipelined access and method for pipelining

Details Memory device having pipelined access and method for pipelining Memory device having pipelined access and method for pipelining

1997-08-22

1999-05-04

Nelms, David

Static information storage and retrieval

Read/write circuit

Signals

365194, 365196, 365205, G11C 700

Patent

active

059010924

ABSTRACT:
In one embodiment of the invention, a word line is coupled to a row of memory cells, and some of the memory cells are accessed before the firing signal has propagated all the way to the back end of the word line. In another embodiment of the invention, a circuit includes a memory row that has a plurality of memory cells, and a word line that is coupled to the memory cells. The word line has a front end and a back end, and is coupled to receive a row-activate signal that propagates from the front end to the back end. The circuit also includes an enable circuit that is operable to prohibit a data transfer to or from a memory cell approximately until the row-activate signal arrives at the memory cell, and is operable to prohibit a data transfer to or from another memory cell approximately until the row-activate signal arrives at the other memory cell.

REFERENCES:
patent: 4811290 (1989-03-01), Watanabe
patent: 5557580 (1996-09-01), Numaga et al.
patent: 5682353 (1997-10-01), Eitan et al.
patent: 5748551 (1998-05-01), Ryan et al.

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