Memory device having open bit line cell structure using...

Details Memory device having open bit line cell structure using... Memory device having open bit line cell structure using...

2007-07-17

2007-07-17

Elms, Richard T. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Testing

C365S203000, C365S230030

Reexamination Certificate

active

11223321

ABSTRACT:
A memory device having an open bit line cell structure uses a wafer burn-in testing scheme and a method for testing the same. The memory device includes a sense amplifier having first and second input terminals; a bit line connected to the first input terminal of the sense amplifier and extended in a first direction; an inverted bit line connected to the second input terminal of the sense amplifier and extended in a second direction; and a voltage supply means for applying the same voltage to the bit line and the inverted bit line in a precharge operation mode and applying a different level voltage to the bit line and the inverted bit line in a burn-in test operation mode. It is possible to efficiently screen defects of memory cells and between bit lines by performing a wafer burn-in test using a wafer burn-in scheme on a memory device having an open bit line cell structure.

REFERENCES:
patent: 4991139 (1991-02-01), Takahashi et al.
patent: 5844833 (1998-12-01), Zagar et al.
patent: 5953275 (1999-09-01), Sugibayashi et al.
patent: 6259638 (2001-07-01), Kim
patent: 6534439 (2003-03-01), Van den Tillaart et al.
patent: 6650584 (2003-11-01), Cowles
patent: 2000-0019078 (2000-04-01), None
English language abstract of Korean Publication No. 2000-0019078.

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