Memory device having high speed sense amplifier comprising...

Static information storage and retrieval – Read/write circuit – Differential sensing

Reexamination Certificate

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C365S207000

Reexamination Certificate

active

11071351

ABSTRACT:
A sense amplifier is constructed to reduce the occurrence of malfunctions in a memory read operation, and thus degraded chip yield, due to increased offset of the sense amplifier with further sealing down. The sense amplifier circuit is constructed with a plurality of pull-down circuits and a pull-up circuit, and a transistor in one of the plurality of pull-down circuits has a constant such as a channel length or a channel width larger than that of a transistor in another pulldown circuit. The pull-down circuit with a larger constant of a transistor is first activated, and then, the other pull-down circuit and the pull-up circuit are activated to perform the read operation.

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Itoh,VLSI Memory Chip Design, Springer, 2001, pp. 195-247.
Hong et al., “An Offset Cancellation Bit-line Sensing Scheme for Low-Voltage DRAM Applications,” ISSCC2002 Dig. Tech. Papers, Session 9, Dram and Ferroelectric Memories 9.2, Feb. 5, 2002, pp. 453-455.
Sims et al., “Charge-Transferred Presensing and Efficiently Precharged Negative Word-Line Schemes for Low-Voltage DRAMs,” 2003 Symposium on VLSI Circuits Dig. Tech. Papers, 2003, pp. 289-292.

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