Memory device having dual power ports and memory system...

Details Memory device having dual power ports and memory system... Memory device having dual power ports and memory system...

2003-03-11

2004-09-28

Lam, David (Department: 2818)

Static information storage and retrieval

Powering

C365S189090, C365S189110

Reexamination Certificate

active

06798709

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to memory devices, and more particularly, the present invention relates to memory devices having dual power ports and to memory systems equipped with memory devices having dual power ports.
A claim of priority is made to Korean Patent Application No. 2002-22682, filed on Apr. 25, 2002, the contents of which are incorporated herein by reference.
2. Description of the Related Art
Currently, most memory systems are equipped to receive an externally supplied power voltage, and to convert the externally supplied power voltage into an internal power voltage. The internal power voltage, which may be higher or lower than the externally supplied power voltage, is used as an operational voltage of internal circuits of the memory system.
FIG. 1
is a block diagram illustrating major components parts of a conventional dynamic random access memory (DRAM) system. As shown, a DRAM system
100
includes a DRAM
130
, a voltage regulator
110
to which an external power voltage VEXT is supplied, and a memory controller
120
. The voltage regulator
110
converts the external power voltage VEXT into a power voltage VCC which is lower than the external power voltage VEXT. For example, the external power voltage VEXT may be 5.0V and the power voltage VCC may be 3.3V. The regulated power voltage VCC is supplied as an operational power voltage to the controller
120
and DRAM
130
. The use of a lower-voltage power voltage VCC is primarily intended to reduce power consumption.
In some cases, for example to compensate for a voltage loss caused by a drop in a transistor threshold voltage, it may be necessary for the DRAM
130
to internally generate an internal power voltage VPP which is higher than the power voltage VCC. The internal power voltage VPP voltage may be used in several DRAM circuit components, particularly those constructed with NMOS transistors, such as a word line driver circuit, a bit line isolation circuit in a shared sense amplifier circuit structure, and/or a data output buffer circuit. Specifically, the word line driver circuit may supply the voltage VPP to a word line to allow data be read from or written to a DRAM cell during a read or write operation, without a threshold voltage loss of a transfer transistor of the cell. The bit line isolation circuit may be supplied with the voltage VPP for full HIGH level data transmission between a bit line and a data line. The output buffer may be supplied with the voltage VPP to sufficiently drive an output high voltage (VOH) level.
U.S. Pat. No. 6,320,457 describes circuits having electric charge pumps for generation of the internal power voltage VPP. However, as is generally known, charge pump circuits are generally inefficient and consume large amounts of current. Also, when employing a given charge pump circuit, the pumping current increases with an increase in the target voltage VPP, while pumping efficiency decreases with an increase in the target voltage VPP. Current consumption of the charge pump circuit is often a critical factor in the overall power performance of a memory device, and it is necessary to adopt a charge pump circuit which has appropriate characteristics for a particular memory device.
SUMMARY OF THE INVENTION
According to one aspect of the invention, a plurality of internal circuits of a memory device are operable at first and second internal voltages, where the first internal voltage is less than the second internal voltage. A first power port of the memory device receives a first power supply voltage, and a second power port of the memory device receives a second power supply voltage, where the first power supply voltage is less than the second power supply voltage. An internal voltage generation circuit of the memory device is selectively operable in either a first mode in which the second internal voltage is generated from the first power supply voltage, or a second mode in which the second internal voltage is generated from the second power supply voltage.
According to another aspect of the present invention, a voltage regulator of a memory system generates a first power supply voltage from a second power supply voltage, where the second power supply voltage is greater than the first power supply voltage. A plurality of internal circuits of a memory device of the memory system are operable at first and second internal voltages, where the first internal voltage is less than the second internal voltage. A first power port of the memory device receives the first power supply voltage, and a second power port of the memory device receives the second power supply voltage. An internal voltage generation circuit of the memory device is selectively operable in either a first mode in which the second internal voltage is generated from the first power supply voltage, or a second mode in which the second internal voltage is generated from the second power supply voltage. A control circuit of the memory system controls an operation of the memory device.
According to still another aspect of the present invention, a first voltage regulator of a memory system generates a first power supply voltage from a second power supply voltage, where the second power supply voltage is greater than the first power supply voltage, and a second voltage regulator of the memory system generates a third power supply voltage from the second power supply voltage, where the third power supply voltage is less than the second power supply voltage and greater than the first power supply voltage. A plurality of internal circuits of a memory device of the memory system are operable at first and second internal voltages, where the first internal voltage is less than the second internal voltage. A first power port of the memory device receives the first power supply voltage, and a second power port of the memory device receives the third power supply voltage. An internal voltage generation circuit of the memory device is selectively operable in either a first mode in which the second internal voltage is generated from the first power supply voltage, or a second mode in which the second internal voltage is generated from the third power supply voltage. A control circuit of the memory system controls an operation of the memory device.


REFERENCES:
patent: 6320457 (2001-11-01), Yang
patent: 6574161 (2003-06-01), Ooishi
patent: 09-006442 (1997-01-01), None

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