Memory device having divided global bit lines

Details Memory device having divided global bit lines Memory device having divided global bit lines

1997-10-30

1999-01-26

Nelms, David C.

Static information storage and retrieval

Interconnection arrangements

Transistors or diodes

36518905, G11C 506

Patent

active

058644970

ABSTRACT:
A memory device having a hierarchical bit line for decreasing the size of a chip, wherein a global bit line is divided into two parts. Switches are provided for selecting the divided global bit lines and sub-bit lines connected to memory cells that store data in a folded bit line structure.

REFERENCES:
patent: 5535172 (1996-07-01), Reddy et al.
patent: 5561626 (1996-10-01), Fujii

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