Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
2005-08-16
2005-08-16
Padmanabhan, Mano (Department: 2189)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C710S035000, C711S105000, C711S167000, C711S217000
Reexamination Certificate
active
06931483
ABSTRACT:
A method comprising reordering a block of n-bit words output from a memory array according to information in certain address bits before outputting at least one n-bit word from a memory device and ignoring said certain address bits before inputting at least one n-bit word into said memory array. The method may additionally comprise examining at least two of the least significant bits of a column address and wherein said reordering is responsive to said examining step. Thus, for reads a specific 8 bit burst is identified by the most significant column address bits while the least significant bits CA0-CA2identify the most critical word and the read wrap sequence after the critical word. For writes, the burst is identified by the most significant column addresses with CA0-CA2being “don't care” bits assumed to be 000.
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Micro)n Technology, Inc.
Namazi Mehdi
Padmanabhan Mano
Thorp Reed & Armstrong LLP
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