Memory device having complete row redundancy

Details Memory device having complete row redundancy Memory device having complete row redundancy

1996-08-08

1998-09-29

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Bad bit

36523006, 365221, G11C 700

Patent

active

058154477

ABSTRACT:
An ATM switch including a multi-port memory is described. The multi-port memory has a dynamic random access memory (DRAM) and input and output serial access memories (SAMs). The multi-port memory includes an array of primary and redundant memory cells. Data transfer buses are described which traverse the array and can be coupled to either the primary or redundant memory cells. Redundant row enable circuitry is described which enables an entire row of redundant memory cells to be substituted for any row of primary memory cells.

REFERENCES:
patent: 5281868 (1994-01-01), Morgan
patent: 5327380 (1994-07-01), Kersh, III et al.
patent: 5361231 (1994-11-01), Hayano
patent: 5508638 (1996-04-01), Cowles et al.
patent: 5513137 (1996-04-01), Lee et al.
patent: 5528539 (1996-06-01), Ong et al.
patent: 5559742 (1996-09-01), Lee et al.

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