Memory device having an evaluation circuit

Details Memory device having an evaluation circuit Memory device having an evaluation circuit

2008-08-29

2010-10-26

Mai, Son L (Department: 2827)

Static information storage and retrieval

Read/write circuit

Flip-flop used for sensing

C365S208000, C327S051000, C327S057000

Reexamination Certificate

active

07821856

ABSTRACT:
A memory device comprising a memory cell and an evaluation circuit, the memory cell being coupled with the evaluation circuit via a bit line. The memory device further comprises a reference line coupled with the evaluation circuit, the evaluation circuit being designed for amplifying a difference between electric potentials of the bit line and the reference line. Inputs of the evaluation circuit are directly connected to the bit line. Outputs of the evaluation circuit are coupled to the bit line via a switch.

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Sanghoon Hong, Sejun Kim, Jae-Kyung Wee and Seongsoo Lee, “Low-Voltage DRAM Sensing Scheme With Offset-Cancellation Sense Amplifier”, IEEE Journal of Solid-State Circuits, vol. 37, No. 10, Oct. 2002, pp. 1356-1360.

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