Memory device having an electron trapping layer in a high-K...

Details Memory device having an electron trapping layer in a high-K... Memory device having an electron trapping layer in a high-K...

2006-01-24

2006-01-24

Mai, Anh Duy (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S325000

Reexamination Certificate

active

06989565

ABSTRACT:
An improved semiconductor memory structure and methods for its fabrication are disclosed. The memory structure includes a semiconductor substrate having a dielectric stack formed over a channel region of a semiconductor substrate. The dielectric stack includes a layer of electron trapping material that operates as a charge storage center for memory devices. A gate electrode is connected with the top of the dielectric stack. In various embodiments the electron trapping material forms a greater or lesser portion of the dielectric stack. The invention includes a method embodiment for forming such a memory device.

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