Memory device having address translator and comparator for compa

Details Memory device having address translator and comparator for compa Memory device having address translator and comparator for compa

1994-12-19

1995-10-31

Gossage, Glenn

Static information storage and retrieval

Magnetic bubbles

Guide structure

365 49, 36523001, 36523006, 364DIG1, 395435, 395410, G06F 1210

Patent

active

054637511

ABSTRACT:
A semiconductor memory device has an address translator and a comparator. An entry of the address translator includes an associative memory cell array for storing and comparing a logical address of at least m bits. A first decoder generates a first word signal for the associative memory cell array. A first random access memory cell array stores a physical address of m bits. A controller generates a word signal for the first random access memory cell according to the first word signal and a result of a comparison by the associative memory cell array. A second random access memory cell stores a physical address of m bits. The second random access memory cell is physically disposed near the first random access memory cell array. A second decoder generates a second word signal for the second random access memory cell array. Outputs of the first and second random access memory cell arrays are connected to and compared by the comparator which outputs a signal upon coincidence between the outputs of the first and second random access memory cell arrays.

REFERENCES:
patent: 4400770 (1983-08-01), Chan et al.
patent: 4430701 (1984-02-01), Christian et al.
patent: 4884197 (1989-11-01), Sachs et al.
patent: 4996641 (1991-02-01), Talgam et al.
patent: 5111389 (1992-05-01), McAuliffe et al.

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