Memory device having a single pass-gate transistor per...

Details Memory device having a single pass-gate transistor per... Memory device having a single pass-gate transistor per...

2008-10-14

2011-11-01

Tran, Andrew Q (Department: 2824)

Static information storage and retrieval

Read/write circuit

Common read and write circuit

C365S189150, C365S189160, C365S190000, C365S205000, C365S208000, C365S203000, C365S189020, C365S189050, C365S230030

Reexamination Certificate

active

08050114

ABSTRACT:
A memory device, and method of operation of such a device, are provided. The memory device comprises an array of memory cells arranged in a plurality of rows and a plurality of columns, at least one bit line being associated with each column. Column multiplexer circuitry is coupled to the plurality of columns, for inputting write data into a selected column during a write operation and for outputting an indication of read data sensed from a selected column during a read operation. The column multiplexer circuitry comprises a single pass gate transistor per bit line, and latch circuitry is then used to detect the read data from the indication of read data output by the column multiplexer circuitry during the read operation, and to store that detected read data. Such an approach provides a particularly area efficient construction for the column multiplexer circuitry whilst enabling correct evaluation of the read data held in the addressed memory cell.

REFERENCES:
patent: 5440506 (1995-08-01), Longway et al.
patent: 7099202 (2006-08-01), Son et al.
patent: 7821866 (2010-10-01), Raghavan et al.
patent: 2010/0091581 (2010-04-01), Van Winkelhoff et al.
Online Publication, Yun, “Memory”,UC San Diego, May 28, 2008, http://paradise.uscd.edu/class/ece165
otes/IecC.pdf.

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