Memory device having a self-test function using sense amplifiers

Details Memory device having a self-test function using sense amplifiers Memory device having a self-test function using sense amplifiers

1999-05-28

2000-11-07

Nelms, David

Static information storage and retrieval

Read/write circuit

Testing

365203, 36523003, 714718, 714719, G11C 700

Patent

active

061445975

ABSTRACT:
A memory device configured to simultaneously write data on all cells on one row of a matrix cell array constituting the memory device in a test mode, based on data latched in sense amplifiers included in the memory device. The memory device includes a pre-charge control unit coupled to a bit line precharge block and a sense amplifier pre-charge block and adapted to control respective pre-charge operations of the bit line precharge block and sense amplifier pre-charge block in a test mode in such a fashion that the pre-charge operations are deactivated in the test mode after an initial data writing operation is completed for one cell, thereby causing data used in the initial data writing operation to be still latched in the sense amplifiers, so that a subsequent data writing operation is repeatedly carried out, word line by word line, using the latched data. In every data writing operation, all cells on one row of the cell array are simultaneously written with data. Accordingly, it is possible to reduce the test data writing time.

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patent: 5351213 (1994-09-01), Nakashima
patent: 5367492 (1994-11-01), Kawamoto et al.
patent: 5508960 (1996-04-01), Pinkham
patent: 5528551 (1996-06-01), Pinkham
patent: 5553029 (1996-09-01), Reohr et al.
patent: 5684748 (1997-11-01), Jang
patent: 5703816 (1997-12-01), Nam et al.

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