Memory device having a relatively wide data bus

Details Memory device having a relatively wide data bus Memory device having a relatively wide data bus

1998-09-02

2000-03-07

Nguyen, Tan T.

Static information storage and retrieval

Read/write circuit

For complementary information

365 63, G11C 700

Patent

active

06034900&

ABSTRACT:
An architecture for a wide data path in a memory device formed in a semiconductor substrate includes an array of memory cells is formed in an array region of the substrate, the array including a plurality of memory cells arranged in rows and columns. A plurality of complementary pairs of digit lines are formed in the array region from a first conductive layer, each complementary pair being coupled to a plurality of memory cells in an associated column. A plurality of word lines are formed in the array region from a second conductive layer, each word line being coupled to each memory cell in an associated row. A plurality of sense amplifiers are formed in a sense amplifier region of the substrate adjacent the array region, each sense amplifier being coupled to an associated pair of complementary digit lines. A plurality of input/output lines are disposed in a third conductive layer formed above the array region, each input/output line coupled to at least one of the sense amplifiers. At least one column select line is disposed in a portion of the third conductive layer formed above the sense-amplifier region, each column select line being coupled to at least some of the sense amplifiers. The memory device also includes a row address decoder, column address decoder, data path circuit, and control circuit that operate in response to signals applied on respective busses to transfer data to and from the memory device. The architecture may be used, for example, in packetized DRAMs. such as SLDRAMs, and in Embedded DRAMs.

REFERENCES:
patent: 4882708 (1989-11-01), Hayakawa et al.
patent: 5293563 (1994-03-01), Ohta
patent: 5367492 (1994-11-01), Kawamoto et al.
patent: 5404335 (1995-04-01), Tobita
patent: 5621679 (1997-04-01), Seo et al.
patent: 5812473 (1998-09-01), Tsai
patent: 5856938 (1999-01-01), Kasai et al.
R. Torrance et al., "A 33GB/s 13.4Mb Integrated Graphics Accelerator and Frame Buffer," IEEE International Solid-State Circuits Conference, 274, 275, 340, and 341, 1998.
Jeffrey Dreibelbis et al., "An ASIC Library Granular DRAM Macro with Built-In Self Test," IEEE International Solid-State Circuits Conference, 58, 59, 74, and 75, 1998.
T. Yabe et al., "A Configurable DRAM Macro Design for 2112 Derivative Organizations to be Synthesized Using a Memory Generator," IEEE International Solid-State Circuits Conference, 56, 57, 72, and 73, 1998.

Affiliated with

Also associated with

Rating

Memory device having a relatively wide data bus does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory device having a relatively wide data bus, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory device having a relatively wide data bus will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-369186