Static information storage and retrieval – Read/write circuit – Parallel read/write
Reexamination Certificate
2005-04-15
2009-12-01
Le, Vu A (Department: 2824)
Static information storage and retrieval
Read/write circuit
Parallel read/write
C365S221000, C365S194000, C365S196000, C365S189150
Reexamination Certificate
active
07626880
ABSTRACT:
A memory device having a memory core is described. The memory device includes a clock receiver circuit, a control interface, a data interface, a delay locked loop circuit, a read pipeline circuit and a circuit to provide an internal clock signal. The clock receiver circuit receives an external clock signal. The control interface receives a command that specifies a read operation to the memory device. The data interface transfers data between the memory device and an external set of signal lines. The delay locked loop circuit, coupled to the clock receiver circuit, to generate the internal clock signal using the external clock signal. The read pipeline circuit provides read data accessed from the memory core to the data interface. The circuit provides the internal clock signal to the read pipeline circuit in response to receipt of the command that specifies the read operation.
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Rambus, Inc.,
Barth Richard M.
Hampel Craig E.
Stark Donald C.
Tsern Ely K.
Le Vu A
Morgan & Lewis & Bockius, LLP
Rambus Inc.
Yang Han
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