Memory device having a non-uniform redundancy decoder arrangemen

Details Memory device having a non-uniform redundancy decoder arrangemen Memory device having a non-uniform redundancy decoder arrangemen

1992-08-13

1993-12-14

Gossage, Glenn

Static information storage and retrieval

Read/write circuit

Bad bit

36523006, 36523003, 371 101, 371 103, G11C 700, G11C 2900, G06F 1120

Patent

active

052709752

ABSTRACT:
A memory device including a non-uniform redundancy decoder has one or more data blocks with each data block having an array of memory cells arranged in addressable rows and columns along row lines and column lines. Each array is configured into sub-blocks with each sub-block comprising a plurality of the memory cells. A given number of repair columns is allocated to a data block. A plurality of column repair decoder circuits are each connected to a repair column. These column repair decoder circuits are programmable with column and row address information corresponding to a section of an array column contianing a defective memory cell to replace the defective cell with a memory cell in one of the repair columns. Different numbers of column repair decoder circuits are connected to the first and second column repair circuits, thereby creating a nonuniform distribution of column repair circuits. A method of assigning the nonuniform redundancy decoders is also disclosed.

REFERENCES:
patent: 4471472 (1984-09-01), Young
patent: 4653050 (1987-03-01), Vaillancourt
patent: 4672581 (1987-06-01), Waller
patent: 4691301 (1987-09-01), Anderson
patent: 4807191 (1989-02-01), Flannagan
patent: 4847810 (1989-07-01), Tagami

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