Electrical computers and digital processing systems: memory – Storage accessing and control
Reexamination Certificate
1994-05-25
2002-03-12
Thai, Tuan V. (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
C711S110000, C711S154000, C711S167000
Reexamination Certificate
active
06356973
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to memory devices and methods of storing and accessing data. More particularly, the invention concerns storage of data streams in a manner that establishes a systematic relationship between the data itself and points used for accessing the data, to provide independent and extremely efficient access to, and dissemination of, the stored data streams.
2. Description of Relevant Background
Consumer demand for enhanced on-site entertainment and information services is on the rise. Examples of such entertainment and information services include so-called “on-demand” video, interactive video games, database research, “home-shopping” and the like. Numerous service providers are currently eager to tap this demand, and are therefore expressing interest in schemes for providing such services to consumers.
In order to be economically practical and viable, a system offering the wide range of information-related services just described should preferably be able to (i) store very large quantities of data at an affordable cost per bit; and (ii) provide for efficient retrieval of the data with a minimal contention between users for any portion of the data.
Memory devices according to the present invention are advantageously utilized for storing information (e.g., information in digital or analog form). The types of information capable of being stored can include video and audio information (e.g., movies, video games, television and other entertainment programs), educational information and programs, scientific and other research-related database information, consumer catalog and home-shopping information, and the like, and are hereinafter referenced generically as “information” or “titles”.
Many such types of information, in order to be useful, require that the data, which together form the information, are provided in a given sequence or order. Examples include audio information, such as speech or musical compositions, visual information, such as paintings and photographs, and audio-visual information, such as movies, television shows and video games. In the case of a movie, for example, a sequential group of still pictures is connected together on a long strip of photographic film. In order to “play back” the movie, the still pictures are moved past a light source in sequence and at a certain speed, and the resulting images are focused onto a screen while the audio portion of the movie is output over speakers. These resulting images will appear to the viewer to be moving. Similarly, music stored on magnetic tape can be “played back” by moving the magnetic tape serially past a playback head of a tape player.
In analogous fashion, according to more recent techniques, digitally stored data may be stored in a memory and accessed in serial fashion to obtain the same result achieved by the more traditional storage formats mentioned above. As such, an assemblage of stored digital data, if “played back” in serial fashion, can reproduce any of the above types of information. A few of the many types of mechanisms used to store digital data are introduced here just by way of example. They include shift registers, charge coupled devices (CCDs), delay lines, read-only memory (ROM) and random-access memory (RAM).
The shift register as a technology has existed for decades.
FIG. 1A
shows a typical shift register arrangement. As illustrated, the shift register
10
is composed of a series of D-flip-flops
11
. The number of flip-flops provided is variable and depends upon the number of bits N to be stored. In operation, clock pulses input at clock input
12
cause the data at the inputs D to transfer to the outputs Q. This clocking causes data supplied bit by bit at the data input
13
to shift right by one flip-flop. After an appropriate number of clock cycles, the data is output bit by bit at the data output
14
.
The shift register illustrated in
FIG. 1B
is another example of a register, namely a recirculating shift register manufactured by Signetics in 1972. As shown, the shift register comprises an input
20
for data, an input selector
21
, a data storage selector
22
composed of logic gates, a shift register
23
, a device selector
24
, an output selector
25
, clock inputs
26
,
27
, a write control
28
, a read control
29
, and a data output
30
. In operation, the shift register is activated by inputting high signals at the device selector
24
. Then, a write enable signal is input to the write control
28
, while clock input
26
receives clock pulses. At the same time, the data to be stored is fed to the input
20
, thereby inputting the data to be stored. When the write control
28
is changed to low, the data storage selector
22
recirculates the stored data through the shift register
23
, thereby storing the data. When it is desired to output the stored data, a read signal to the read control
29
and clock pulses to the clock input
27
trigger the output selector
25
to output the data stored in the shift register at output
30
. Since the output operation does not damage the recirculating data, the output operation can be performed repeatedly for the same stored data. To alter the data stored in the register, it must be over-written with new data by a write operation, as described above. The storage capacity for this type of shift register is 512 or 1024 binary digits (bits).
Prior art delay lines, such as the one shown in
FIG. 1C
, are composed of a silicon substrate
31
, a signal input
32
, several signal taps
33
spaced equally along the substrate
31
, and a signal output
34
. An electrical signal entering the delay line at the input
32
propagates through the substrate
31
at a fixed, predetermined velocity. While propagating, the signal passes by each of the several taps
33
, which can be used to access the data. Thus, it becomes possible to delay the propagating signal a predetermined amount of time by passing it through the delay line and then selecting an appropriate tap that corresponds to the amount of desired delay. Once the propagating signal reaches the end of the substrate, it is output from the delay line at
34
.
FIGS. 1D and 1E
show a CCD, where
FIG. 1D
is a schematic circuit diagram and
FIG. 1E
is a structural diagram. As shown in
FIG. 1D
, the CCD is composed of metal oxide semiconductor field effect transistors (MOSFETs)
40
connected in series. Amplifiers
41
,
42
, also composed of MOSFETs, are provided on the CCD input and the CCD output, respectively. The CCD operates similarly to the shift register (see
FIG. 1A
) in that a signal enters the CCD at the input
41
and progresses through the CCD from MOSFET to MOSFET in accordance with clock pulses supplied at clock inputs
43
and
44
. After proceeding through the series of MOSFETs
40
, the signal exits the CCD at output
42
. As shown in
FIG. 1E
, the individual MOSFETs are formed by placing metal contact layers
45
at appropriate locations on a semiconductor substrate
46
.
A typical RAM is illustrated in FIG.
1
F. As shown in the drawing, an array of memory cells
50
is connected to respective series of row selectors
51
, column selectors
52
, write amplifiers
53
, and sense amplifiers
54
. In a data load operation, a particular cell to be written to is selected by providing the cell's appropriate column and row address, using the selectors
51
and
52
. The data to be written to that cell is then input to the array
50
via the write amplifiers
53
. Given the prior selection operation, however, the data is stored only in the selected cell. Similarly, in a data read operation, a particular cell to be read is again selected by providing appropriate column and row addresses via the selectors
51
and
52
. The data is then copied out from the array
50
via the sense amplifiers
54
.
FIG. 1G
illustrates a typical ROM. The structure is very similar to that of the RAM just described. An array of pre-set memory cells
60
is connected to respective series of row selectors
61
, c
Bullen M. James
McLaughlin Robert B.
Plumhoff Lawrence C.
Image Telecommunications Corporation
Lehnigk, Esq. George F.
Sughrue Mion Zinn Macpeak & Seas, PLLC
Thai Tuan V.
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